Recieving the following error: "line 36 expecting 'endmodule', found 'if'

Question

在 if(lr == 0) 线上，我收到以下错误“期待 'endmodule'，找到 'if'。Verilog 代码是一个 8 位移位寄存器，它起作用作为左移和右移器，可以在算术和逻辑移位之间进行选择。我不明白为什么会收到错误。这可能是某种语法错误，因为我是 Verilog 的新手。提前感谢您的帮助。

module shifter(
input [7:0] shift_in,
input [2:0] shift_by,

 // 0 for left, 1 for right
input lr,

 //0 for logical, 1 for arithmetic
input arith,
output reg signed [7:0] shift_out
);

//left shift
if(lr == 0) 
begin
    assign shift_out = shift_in << shift_by;
    assign shift_out[0] = 1'b0;
end
//right shift
else begin
    //logical shift
    if (arith == 0) begin
        assign shift_out = shift_in << shift_by;
        assign shift_out[7] = 1'b0;
    //arithmetic shift
    end else begin
        assign shift_out[7] = shift_in[7];
        assign shift_out = shift_in << shift_by;
    end
end

endmodule

Answer 1

您不能将 if 语句与 assign 一起使用。放置在 always 块中并删除分配。

always @* begin
//left shift
if(lr == 1'b0) 
begin
    shift_out = shift_in << shift_by;
    shift_out[0] = 1'b0;
end
//right shift
else begin
    //logical shift
    if (arith == 0) begin
        shift_out = shift_in << shift_by;
        shift_out[7] = 1'b0;
    //arithmetic shift
    end else begin
        shift_out[7] = shift_in[7];
        shift_out = shift_in << shift_by;
    end
end
end

Recieving the following error: "line 36 expecting 'endmodule', found 'if'

Recieving the following error: "line 36 expecting 'endmodule', found 'if'

syntax

verilog