在同一个 verilog 文件中声明任务

Question

我试图在测试台中声明一个简单的时钟摆动任务，但 ModelSim 声称不存在我的任务类型的设计元素。这段代码有什么问题：

`timescale 1 ns/1 ns

module at25320a_tester();
    reg clk, s_in, s_out, chip_select, write_protect, hold;

    // Instantiate at25320a module
    at25320a EEPROM (.SCK(clk), .SI(s_in), .CSNeg(chip_select), .HOLDNeg(hold), .WPNeg(write_protect), .SO(s_out));

    run_clk(15);

    task run_clk;
        input [3:0] cycles;
        output reg clk;

        integer i;

        for (i=0;i<cycles;i=i+1) begin
            #100 clk = 1;
            #100 clk = 0;
        end
    endtask

endmodule

Answer 1

必须从程序块调用任务，例如 always 或 initial。在您的情况下，您需要运行 initial 块中的任务并进行一些修改：

`timescale 1 ns/1 ns

module at25320a_tester();
    reg clk, s_in, s_out, chip_select, write_protect, hold;

    // Instantiate at25320a module
    at25320a EEPROM (.SCK(clk), .SI(s_in), .CSNeg(chip_select), .HOLDNeg(hold), .WPNeg(write_protect), .SO(s_out));

    initial begin
        run_clk(15);
    end

    task run_clk;
        input integer cycles; // Might as well not have this be bigger
        // No clock, you want to use the clock from the module
        integer i;

        for (i=0;i<cycles;i=i+1) begin
            #100 clk = 1;
            #100 clk = 0;
        end
    endtask

endmodule

在同一个 verilog 文件中声明任务

Declaring task in same verilog file

verilog

modelsim