班次添加单元代码

Question

我写了移位加法器单元的代码....但我没有得到正确的结果...在这里我不能 post ckt 同样...我认为那里有 clk 同步问题

 module shift_adder_8a(clk,,j0,j7,s089,s075,s050,s018);
input clk;
input [2:0] j0,j7;
 reg[3:0]z0;
output reg[10:0]s089,s075,s050,s018;
reg[6:0] o0,p0;

always@(posedge clk )
begin
 z0 <= j0-j7;
 o0 <= (z0<<3)+z0;
 p0 <=  (z0<<4)+o0;
 s089 <= (z0<<6)+p0;
 s075 <= (p0<<1)+p0;
 s050 <= (p0<<1);
 s018 <= (o0<<1);

 end
endmodule

Answer 1

不是 "get correct result"，我假设你的意思是结果会延迟。

尝试将 z0、o0、p0 赋值移动到组合块中：

always @* begin
 z0 = j0-j7;
 o0 = (z0<<3)+z0;
 p0 = (z0<<4)+o0;
end
always@(posedge clk )
begin
 s089 <= (z0<<6)+p0;
 s075 <= (p0<<1)+p0;
 s050 <= (p0<<1);
 s018 <= (o0<<1);
end

班次添加单元代码

code for shift add unit

verilog

system-verilog