VHDL 仿真不显示波形
VHDL simulation does not display a waveform
我用 VHDL 编写代码，并使用 Active HDL Student Edition 来编译和使用测试平台模拟代码。当我模拟 500ns 时，信号发生变化，但波形上的信号卡在 U 上，没有任何显示。我似乎找不到导致此问题的原因。
这是我的实体代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity idexreg is
port(
rst_bar : in std_logic;
clk : in std_logic;
immediate_in : in std_logic_vector(63 downto 0);
reg0_in : in std_logic_vector(63 downto 0);
reg1_in : in std_logic_vector(63 downto 0);
instruction_in : in std_logic_vector(3 downto 0);
pc_in : in std_logic_vector(3 downto 0);
immediate_out : out std_logic_vector(63 downto 0);
reg0_out : out std_logic_vector(63 downto 0);
reg1_out : out std_logic_vector(63 downto 0);
instruction_out : out std_logic_vector(3 downto 0);
pc_out : out std_logic_vector(3 downto 0)
);
end idexreg;
architecture idexreg_arch of idexreg is
begin
arch: process(clk, rst_bar)
begin
if rst_bar = '0' then
immediate_out <= std_logic_vector(x"0000000000000000");
reg0_out <= std_logic_vector(x"0000000000000000");
reg1_out <= std_logic_vector(x"0000000000000000");
instruction_out <= std_logic_vector(x"0");
pc_out <= std_logic_vector(x"0");
elsif falling_edge(clk) then
immediate_out <= immediate_in;
reg0_out <= reg0_in;
reg1_out <= reg1_in;
instruction_out <= instruction_in;
pc_out <= pc_in;
end if;
end process;
end idexreg_arch;
这是测试平台的代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
entity idexreg_tb is
end idexreg_tb;
architecture test of idexreg_tb is
--input signals
signal rst_bar : std_logic;
signal clk: std_logic;
signal immediate_in : std_logic_vector(63 downto 0);
signal reg0_in : std_logic_vector(63 downto 0);
signal reg1_in : std_logic_vector(63 downto 0);
signal instruction_in : std_logic_vector(3 downto 0);
signal pc_in : std_logic_vector(3 downto 0);
--output signals
signal immediate_out : std_logic_vector(63 downto 0);
signal reg0_out : std_logic_vector(63 downto 0);
signal reg1_out : std_logic_vector(63 downto 0);
signal instruction_out : std_logic_vector(3 downto 0);
signal pc_out : std_logic_vector(3 downto 0);
-- boolean to signify end of simulation
signal end_sim : boolean := false;
constant period : time := 50ns;
begin
UUT: entity idexreg
port map(
rst_bar => rst_bar,
clk => clk,
immediate_in => immediate_in,
reg0_in => reg0_in,
reg1_in => reg1_in,
instruction_in => instruction_in,
pc_in => pc_in,
immediate_out => immediate_out,
reg0_out => reg0_out,
reg1_out => reg1_out,
instruction_out => instruction_out,
pc_out => pc_out);
-- Generate the Clock signal
clk_gen: process
begin
clk <= '0';
loop
wait for period/2;
clk <= not clk;
exit when end_sim = true;
end loop;
wait;
end process;
stim: process
begin
-- reset the register file first
rst_bar <= '0';
wait for 100ns;
rst_bar <= '1';
--Test 1
immediate_in <= std_logic_vector(x"AAAAAAAAAAAAAAAA");
reg0_in <= std_logic_vector(x"AAAAAAAAAAAAAAAA");
reg1_in <= std_logic_vector(x"AAAAAAAAAAAAAAAA");
instruction_in <= std_logic_vector(x"A");
pc_in <= std_logic_vector(x"1");
wait for 10ns;
--Test 2
immediate_in <= std_logic_vector(x"BBBBBBBBBBBBBBBB");
reg0_in <= std_logic_vector(x"BBBBBBBBBBBBBBBB");
reg1_in <= std_logic_vector(x"BBBBBBBBBBBBBBBB");
instruction_in <= std_logic_vector(x"B");
pc_in <= std_logic_vector(x"2");
wait for 30ns;
--Test 3
immediate_in <= std_logic_vector(x"CCCCCCCCCCCCCCCC");
reg0_in <= std_logic_vector(x"CCCCCCCCCCCCCCCC");
reg1_in <= std_logic_vector(x"CCCCCCCCCCCCCCCC");
instruction_in <= std_logic_vector(x"C");
pc_in <= std_logic_vector(x"3");
end_sim <= true;
wait;
end process;
end test;
如有任何帮助，我们将不胜感激！
在另外两个符合标准的模拟器中发现三个 类 错误。
语义错误:
UUT: entity idexreg
应该是
UUT: entity work.idexreg
如果没有 use 子句 use.work.all;，先前分析的实体 idexreg 的声明将不可见（未绑定，这将说明“U”）。当名称不直接可见时，可以使用选定的名称。
IEEE 标准 1076-2008 12.3 可见性
The meaning of the occurrence of an identifier at a given place in the text is defined by the visibility rules and also, in the case of overloaded declarations, by the overloading rules. The identifiers considered in this subclause include any identifier other than a reserved word or an attribute designator that denotes a predefined attribute. The places considered in this subclause are those where a lexical element (such as an identifier) occurs. The overloaded declarations considered in this subclause are those for subprograms and enumeration literals.
12.4 使用子句
A use clause achieves direct visibility of declarations that are visible by selection.
（如上所示的修复）
13.2 设计库
Every design unit except a context declaration and package STANDARD is assumed to contain the following implicit context items as part of its context clause:
library STD, WORK; use STD.STANDARD.all;
请注意，库名称 WORK 由 library 子句直接可见，但如果没有 use 子句，则分析到库工作中的设计单元不会直接可见。
返回 12.4 使用子句：
Each selected name in a use clause identifies one or more declarations that will potentially become directly visible. If the suffix of the selected name is a simple name other than a type mark, or is a character literal or operator symbol, then the selected name identifies only the declaration(s) of that simple name, character literal, or operator symbol contained within the package or library denoted by the prefix of the selected name.
...
If the suffix is the reserved word all, then the selected name identifies all declarations that are contained within the package or library denoted by the prefix of the selected name.
还有两个额外的错误 类，第一个是您的模拟器不需要遵守设计说明。
一、语法规则：
15.3 词汇元素、分隔符和定界符
At least one separator is required between an identifier or an abstract literal and an adjacent identifier or abstract literal.
至少有一个成功的商业模拟器忽略了这条规则。 -2008 年更难忽略它。
第二种，又一个语义规则：
9.3.6 类型转换
— Array types—Two array types are closely related if and only if the types have the same dimensionality and the element types are closely related
字符串与std_logic_vector类型转换关系不密切。您可以删除不需要的类型转换 - 位串的类型来自上下文：
9.3.6:
The type of the operand of a type conversion shall be determined by applying the rules of 12.5 to the operand considered as a complete context.
这意味着您看到的只是扩展的位串 (15.8)，例如：
std_logic_vector(x"0000000000000000")
作为字符串，具有字符元素类型的数组类型，而 std_logic_vector 具有 std_ulogic 或 std_logic 元素类型（取决于 VHDL 版本）。这意味着类型转换的操作数和类型标记没有密切关系。
不应忽略此规则。
9.3.2 文字
String and bit string literals are representations of one-dimensional arrays of characters. The type of a string or bit string literal shall be determinable solely from the context in which the literal appears, excluding the literal itself but using the fact that the type of the literal shall be a one-dimensional array of a character type. The lexical structure of string and bit string literals is defined in Clause 15.
您同样可以使用限定表达式。
9.3.5 限定表达式
A qualified expression is a basic operation (see 5.1) that is used to explicitly state the type, and possibly the subtype, of an operand that is an expression or an aggregate.
两种方法如下所示，口述所需的工作量已更改为限定表达式，仅需要额外的 ' 个字符。
然后您的代码将在任何符合标准的 VHDL 工具上成功分析：
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity idexreg is
port(
rst_bar : in std_logic;
clk : in std_logic;
immediate_in : in std_logic_vector(63 downto 0);
reg0_in : in std_logic_vector(63 downto 0);
reg1_in : in std_logic_vector(63 downto 0);
instruction_in : in std_logic_vector(3 downto 0);
pc_in : in std_logic_vector(3 downto 0);
immediate_out : out std_logic_vector(63 downto 0);
reg0_out : out std_logic_vector(63 downto 0);
reg1_out : out std_logic_vector(63 downto 0);
instruction_out : out std_logic_vector(3 downto 0);
pc_out : out std_logic_vector(3 downto 0)
);
end idexreg;
architecture idexreg_arch of idexreg is
begin
arch: process(clk, rst_bar)
begin
if rst_bar = '0' then
immediate_out <= std_logic_vector'(x"0000000000000000");
reg0_out <= std_logic_vector'(x"0000000000000000");
reg1_out <= std_logic_vector'(x"0000000000000000");
instruction_out <= std_logic_vector'(x"0");
pc_out <= std_logic_vector'(x"0");
elsif falling_edge(clk) then
immediate_out <= immediate_in;
reg0_out <= reg0_in;
reg1_out <= reg1_in;
instruction_out <= instruction_in;
pc_out <= pc_in;
end if;
end process;
end idexreg_arch;
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee.std_logic_arith.all;
entity idexreg_tb is
end idexreg_tb;
architecture test of idexreg_tb is
--input signals
signal rst_bar : std_logic;
signal clk: std_logic;
signal immediate_in : std_logic_vector(63 downto 0);
signal reg0_in : std_logic_vector(63 downto 0);
signal reg1_in : std_logic_vector(63 downto 0);
signal instruction_in : std_logic_vector(3 downto 0);
signal pc_in : std_logic_vector(3 downto 0);
--output signals
signal immediate_out : std_logic_vector(63 downto 0);
signal reg0_out : std_logic_vector(63 downto 0);
signal reg1_out : std_logic_vector(63 downto 0);
signal instruction_out : std_logic_vector(3 downto 0);
signal pc_out : std_logic_vector(3 downto 0);
-- boolean to signify end of simulation
signal end_sim : boolean := false;
constant period : time := 50 ns;
begin
UUT: entity work.idexreg -- ERROR HERE was entity idexreg
port map (
rst_bar => rst_bar,
clk => clk,
immediate_in => immediate_in,
reg0_in => reg0_in,
reg1_in => reg1_in,
instruction_in => instruction_in,
pc_in => pc_in,
immediate_out => immediate_out,
reg0_out => reg0_out,
reg1_out => reg1_out,
instruction_out => instruction_out,
pc_out => pc_out);
-- Generate the Clock signal
clk_gen: process
begin
clk <= '0';
loop
wait for period/2;
clk <= not clk;
exit when end_sim = true;
end loop;
wait;
end process;
stim: process
begin
-- reset the register file first
rst_bar <= '0';
wait for 100 ns;
rst_bar <= '1';
--Test 1
immediate_in <= x"AAAAAAAAAAAAAAAA"; -- std_logic_vector'(x"AAAAAAAAAAAAAAAA");
reg0_in <= std_logic_vector'(x"AAAAAAAAAAAAAAAA");
reg1_in <= std_logic_vector'(x"AAAAAAAAAAAAAAAA");
instruction_in <= std_logic_vector'(x"A");
pc_in <= std_logic_vector'(x"1");
wait for 10 ns;
--Test 2
immediate_in <= std_logic_vector'(x"BBBBBBBBBBBBBBBB");
reg0_in <= std_logic_vector'(x"BBBBBBBBBBBBBBBB");
reg1_in <= std_logic_vector'(x"BBBBBBBBBBBBBBBB");
instruction_in <= std_logic_vector'(x"B");
pc_in <= std_logic_vector'(x"2");
wait for 30 ns;
--Test 3
immediate_in <= std_logic_vector'(x"CCCCCCCCCCCCCCCC");
reg0_in <= std_logic_vector'(x"CCCCCCCCCCCCCCCC");
reg1_in <= std_logic_vector'(x"CCCCCCCCCCCCCCCC");
instruction_in <= std_logic_vector'(x"C");
pc_in <= std_logic_vector'(x"3");
end_sim <= true;
wait;
end process;
end test;
修复上述错误会给你带来除“U”之外的东西：
.
immediate_in 是测试 1 中的信号赋值，它没有使用限定表达式，而是依赖于 9.3.2 的规则来确定位串文字的类型。最里面的complete context (12.5) 用来判断位串字面量类型的就是赋值语句本身
分配 immediate_in 的方法通常被广泛用作首选方法。类型取自赋值的目标。
我用 VHDL 编写代码，并使用 Active HDL Student Edition 来编译和使用测试平台模拟代码。当我模拟 500ns 时，信号发生变化，但波形上的信号卡在 U 上，没有任何显示。我似乎找不到导致此问题的原因。
这是我的实体代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity idexreg is
port(
rst_bar : in std_logic;
clk : in std_logic;
immediate_in : in std_logic_vector(63 downto 0);
reg0_in : in std_logic_vector(63 downto 0);
reg1_in : in std_logic_vector(63 downto 0);
instruction_in : in std_logic_vector(3 downto 0);
pc_in : in std_logic_vector(3 downto 0);
immediate_out : out std_logic_vector(63 downto 0);
reg0_out : out std_logic_vector(63 downto 0);
reg1_out : out std_logic_vector(63 downto 0);
instruction_out : out std_logic_vector(3 downto 0);
pc_out : out std_logic_vector(3 downto 0)
);
end idexreg;
architecture idexreg_arch of idexreg is
begin
arch: process(clk, rst_bar)
begin
if rst_bar = '0' then
immediate_out <= std_logic_vector(x"0000000000000000");
reg0_out <= std_logic_vector(x"0000000000000000");
reg1_out <= std_logic_vector(x"0000000000000000");
instruction_out <= std_logic_vector(x"0");
pc_out <= std_logic_vector(x"0");
elsif falling_edge(clk) then
immediate_out <= immediate_in;
reg0_out <= reg0_in;
reg1_out <= reg1_in;
instruction_out <= instruction_in;
pc_out <= pc_in;
end if;
end process;
end idexreg_arch;
这是测试平台的代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
entity idexreg_tb is
end idexreg_tb;
architecture test of idexreg_tb is
--input signals
signal rst_bar : std_logic;
signal clk: std_logic;
signal immediate_in : std_logic_vector(63 downto 0);
signal reg0_in : std_logic_vector(63 downto 0);
signal reg1_in : std_logic_vector(63 downto 0);
signal instruction_in : std_logic_vector(3 downto 0);
signal pc_in : std_logic_vector(3 downto 0);
--output signals
signal immediate_out : std_logic_vector(63 downto 0);
signal reg0_out : std_logic_vector(63 downto 0);
signal reg1_out : std_logic_vector(63 downto 0);
signal instruction_out : std_logic_vector(3 downto 0);
signal pc_out : std_logic_vector(3 downto 0);
-- boolean to signify end of simulation
signal end_sim : boolean := false;
constant period : time := 50ns;
begin
UUT: entity idexreg
port map(
rst_bar => rst_bar,
clk => clk,
immediate_in => immediate_in,
reg0_in => reg0_in,
reg1_in => reg1_in,
instruction_in => instruction_in,
pc_in => pc_in,
immediate_out => immediate_out,
reg0_out => reg0_out,
reg1_out => reg1_out,
instruction_out => instruction_out,
pc_out => pc_out);
-- Generate the Clock signal
clk_gen: process
begin
clk <= '0';
loop
wait for period/2;
clk <= not clk;
exit when end_sim = true;
end loop;
wait;
end process;
stim: process
begin
-- reset the register file first
rst_bar <= '0';
wait for 100ns;
rst_bar <= '1';
--Test 1
immediate_in <= std_logic_vector(x"AAAAAAAAAAAAAAAA");
reg0_in <= std_logic_vector(x"AAAAAAAAAAAAAAAA");
reg1_in <= std_logic_vector(x"AAAAAAAAAAAAAAAA");
instruction_in <= std_logic_vector(x"A");
pc_in <= std_logic_vector(x"1");
wait for 10ns;
--Test 2
immediate_in <= std_logic_vector(x"BBBBBBBBBBBBBBBB");
reg0_in <= std_logic_vector(x"BBBBBBBBBBBBBBBB");
reg1_in <= std_logic_vector(x"BBBBBBBBBBBBBBBB");
instruction_in <= std_logic_vector(x"B");
pc_in <= std_logic_vector(x"2");
wait for 30ns;
--Test 3
immediate_in <= std_logic_vector(x"CCCCCCCCCCCCCCCC");
reg0_in <= std_logic_vector(x"CCCCCCCCCCCCCCCC");
reg1_in <= std_logic_vector(x"CCCCCCCCCCCCCCCC");
instruction_in <= std_logic_vector(x"C");
pc_in <= std_logic_vector(x"3");
end_sim <= true;
wait;
end process;
end test;
如有任何帮助，我们将不胜感激！
在另外两个符合标准的模拟器中发现三个 类 错误。
语义错误:
UUT: entity idexreg
应该是
UUT: entity work.idexreg
如果没有 use 子句 use.work.all;，先前分析的实体 idexreg 的声明将不可见（未绑定，这将说明“U”）。当名称不直接可见时，可以使用选定的名称。
IEEE 标准 1076-2008 12.3 可见性
The meaning of the occurrence of an identifier at a given place in the text is defined by the visibility rules and also, in the case of overloaded declarations, by the overloading rules. The identifiers considered in this subclause include any identifier other than a reserved word or an attribute designator that denotes a predefined attribute. The places considered in this subclause are those where a lexical element (such as an identifier) occurs. The overloaded declarations considered in this subclause are those for subprograms and enumeration literals.
12.4 使用子句
A use clause achieves direct visibility of declarations that are visible by selection.
（如上所示的修复）
13.2 设计库
Every design unit except a context declaration and package STANDARD is assumed to contain the following implicit context items as part of its context clause:
library STD, WORK; use STD.STANDARD.all;
请注意，库名称 WORK 由 library 子句直接可见，但如果没有 use 子句，则分析到库工作中的设计单元不会直接可见。
返回 12.4 使用子句：
Each selected name in a use clause identifies one or more declarations that will potentially become directly visible. If the suffix of the selected name is a simple name other than a type mark, or is a character literal or operator symbol, then the selected name identifies only the declaration(s) of that simple name, character literal, or operator symbol contained within the package or library denoted by the prefix of the selected name.
...
If the suffix is the reserved word all, then the selected name identifies all declarations that are contained within the package or library denoted by the prefix of the selected name.
还有两个额外的错误 类，第一个是您的模拟器不需要遵守设计说明。
一、语法规则：
15.3 词汇元素、分隔符和定界符
At least one separator is required between an identifier or an abstract literal and an adjacent identifier or abstract literal.
至少有一个成功的商业模拟器忽略了这条规则。 -2008 年更难忽略它。
第二种，又一个语义规则：
9.3.6 类型转换
— Array types—Two array types are closely related if and only if the types have the same dimensionality and the element types are closely related
字符串与std_logic_vector类型转换关系不密切。您可以删除不需要的类型转换 - 位串的类型来自上下文：
9.3.6:
The type of the operand of a type conversion shall be determined by applying the rules of 12.5 to the operand considered as a complete context.
这意味着您看到的只是扩展的位串 (15.8)，例如：
std_logic_vector(x"0000000000000000")
作为字符串，具有字符元素类型的数组类型，而 std_logic_vector 具有 std_ulogic 或 std_logic 元素类型（取决于 VHDL 版本）。这意味着类型转换的操作数和类型标记没有密切关系。
不应忽略此规则。
9.3.2 文字
String and bit string literals are representations of one-dimensional arrays of characters. The type of a string or bit string literal shall be determinable solely from the context in which the literal appears, excluding the literal itself but using the fact that the type of the literal shall be a one-dimensional array of a character type. The lexical structure of string and bit string literals is defined in Clause 15.
您同样可以使用限定表达式。
9.3.5 限定表达式
A qualified expression is a basic operation (see 5.1) that is used to explicitly state the type, and possibly the subtype, of an operand that is an expression or an aggregate.
两种方法如下所示，口述所需的工作量已更改为限定表达式，仅需要额外的 ' 个字符。
然后您的代码将在任何符合标准的 VHDL 工具上成功分析：
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity idexreg is
port(
rst_bar : in std_logic;
clk : in std_logic;
immediate_in : in std_logic_vector(63 downto 0);
reg0_in : in std_logic_vector(63 downto 0);
reg1_in : in std_logic_vector(63 downto 0);
instruction_in : in std_logic_vector(3 downto 0);
pc_in : in std_logic_vector(3 downto 0);
immediate_out : out std_logic_vector(63 downto 0);
reg0_out : out std_logic_vector(63 downto 0);
reg1_out : out std_logic_vector(63 downto 0);
instruction_out : out std_logic_vector(3 downto 0);
pc_out : out std_logic_vector(3 downto 0)
);
end idexreg;
architecture idexreg_arch of idexreg is
begin
arch: process(clk, rst_bar)
begin
if rst_bar = '0' then
immediate_out <= std_logic_vector'(x"0000000000000000");
reg0_out <= std_logic_vector'(x"0000000000000000");
reg1_out <= std_logic_vector'(x"0000000000000000");
instruction_out <= std_logic_vector'(x"0");
pc_out <= std_logic_vector'(x"0");
elsif falling_edge(clk) then
immediate_out <= immediate_in;
reg0_out <= reg0_in;
reg1_out <= reg1_in;
instruction_out <= instruction_in;
pc_out <= pc_in;
end if;
end process;
end idexreg_arch;
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee.std_logic_arith.all;
entity idexreg_tb is
end idexreg_tb;
architecture test of idexreg_tb is
--input signals
signal rst_bar : std_logic;
signal clk: std_logic;
signal immediate_in : std_logic_vector(63 downto 0);
signal reg0_in : std_logic_vector(63 downto 0);
signal reg1_in : std_logic_vector(63 downto 0);
signal instruction_in : std_logic_vector(3 downto 0);
signal pc_in : std_logic_vector(3 downto 0);
--output signals
signal immediate_out : std_logic_vector(63 downto 0);
signal reg0_out : std_logic_vector(63 downto 0);
signal reg1_out : std_logic_vector(63 downto 0);
signal instruction_out : std_logic_vector(3 downto 0);
signal pc_out : std_logic_vector(3 downto 0);
-- boolean to signify end of simulation
signal end_sim : boolean := false;
constant period : time := 50 ns;
begin
UUT: entity work.idexreg -- ERROR HERE was entity idexreg
port map (
rst_bar => rst_bar,
clk => clk,
immediate_in => immediate_in,
reg0_in => reg0_in,
reg1_in => reg1_in,
instruction_in => instruction_in,
pc_in => pc_in,
immediate_out => immediate_out,
reg0_out => reg0_out,
reg1_out => reg1_out,
instruction_out => instruction_out,
pc_out => pc_out);
-- Generate the Clock signal
clk_gen: process
begin
clk <= '0';
loop
wait for period/2;
clk <= not clk;
exit when end_sim = true;
end loop;
wait;
end process;
stim: process
begin
-- reset the register file first
rst_bar <= '0';
wait for 100 ns;
rst_bar <= '1';
--Test 1
immediate_in <= x"AAAAAAAAAAAAAAAA"; -- std_logic_vector'(x"AAAAAAAAAAAAAAAA");
reg0_in <= std_logic_vector'(x"AAAAAAAAAAAAAAAA");
reg1_in <= std_logic_vector'(x"AAAAAAAAAAAAAAAA");
instruction_in <= std_logic_vector'(x"A");
pc_in <= std_logic_vector'(x"1");
wait for 10 ns;
--Test 2
immediate_in <= std_logic_vector'(x"BBBBBBBBBBBBBBBB");
reg0_in <= std_logic_vector'(x"BBBBBBBBBBBBBBBB");
reg1_in <= std_logic_vector'(x"BBBBBBBBBBBBBBBB");
instruction_in <= std_logic_vector'(x"B");
pc_in <= std_logic_vector'(x"2");
wait for 30 ns;
--Test 3
immediate_in <= std_logic_vector'(x"CCCCCCCCCCCCCCCC");
reg0_in <= std_logic_vector'(x"CCCCCCCCCCCCCCCC");
reg1_in <= std_logic_vector'(x"CCCCCCCCCCCCCCCC");
instruction_in <= std_logic_vector'(x"C");
pc_in <= std_logic_vector'(x"3");
end_sim <= true;
wait;
end process;
end test;
修复上述错误会给你带来除“U”之外的东西：
immediate_in 是测试 1 中的信号赋值，它没有使用限定表达式，而是依赖于 9.3.2 的规则来确定位串文字的类型。最里面的complete context (12.5) 用来判断位串字面量类型的就是赋值语句本身
分配 immediate_in 的方法通常被广泛用作首选方法。类型取自赋值的目标。