Verilog 算术和逻辑单元 (ALU) 编译错误

Question

我遇到这样的编译错误：

Error (10663): Verilog HDL Port Connection error at jdb_Blogic_v.v(7): output or inout port "f" must be connected to a structural net expression

我评论了有错误的行。我该如何解决？

我还包含了 mux2to1 功能代码。

module jdb_Blogic_v (FS2_in, FS1_in, B_in, Y_out);

input FS2_in, FS1_in;
input [3:0] B_in;
output reg [3:0] Y_out;

jdb_mux2to1_v stage0 (B_in[0], FS1_in, FS2_in, Y_out[0]); //ERROR IS HERE ACCORDING TO COMPILER
jdb_mux2to1_v stage1 (B_in[1], FS1_in, FS2_in, Y_out[1]);
jdb_mux2to1_v stage2 (B_in[2], FS1_in, FS2_in, Y_out[2]);
jdb_mux2to1_v stage3 (B_in[3], FS1_in, FS2_in, Y_out[3]);

endmodule



module jdb_mux2to1_v (s, x1, x2, f);

input x1, x2, s;
output f;
wire    k, g, h;

not (k, s);
and (g, k, x1);
and (h, s, x2);
or (f, g, h);

endmodule

Answer 1

将 Y_out 的声明从 output reg [3:0] 更改为 output [3:0]。这会将其从 reg 更改为 wire。

reg 只能从程序语句中赋值，例如 always 块。

Verilog 算术和逻辑单元 (ALU) 编译错误

Verilog Arithmetic and Logic Unit (ALU) Compilation Error

verilog

digital