这是一个前瞻加法器吗？以及如何对其进行基准测试？

Question

我试图同时制作纹波进位和前瞻 N 位加法器，当我制作 N 位全加器时，我决定将它重新用于前瞻，但就是感觉不到适合我。

全加器：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FullAdder is
    Port ( 
        FA_A    : in  STD_LOGIC;
        FA_B    : in  STD_LOGIC;
        FA_Cin  : in  STD_LOGIC;
        FA_S    : out STD_LOGIC;
        FA_Cout : out STD_LOGIC
    );
end FullAdder;

architecture Behavior of FullAdder is 
begin
    FA_S    <= FA_A XOR FA_B XOR FA_Cin ;
    FA_Cout <= (FA_A AND FA_B) OR (FA_Cin AND FA_A) OR (FA_Cin AND FA_B);
end Behavior;

N 位块：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FullAdderNBits is

    Generic( N : integer  := 8 );

    Port ( 
        A    : in  STD_LOGIC_VECTOR(0 to N-1);
        B    : in  STD_LOGIC_VECTOR(0 to N-1);
        Cin  : in  STD_LOGIC;
        S    : out STD_LOGIC_VECTOR(0 to N-1);
        Cout : out STD_LOGIC
    );

end FullAdderNBits;

architecture Behavior of FullAdderNBits is
    signal temp_B     : STD_LOGIC_VECTOR(0 to N-1);
    signal carries    : STD_LOGIC_VECTOR(0 to N);

    component FullAdder Port(
            FA_A    : in  STD_LOGIC;
            FA_B    : in  STD_LOGIC;
            FA_Cin  : in  STD_LOGIC;
            FA_S    : out STD_LOGIC;
            FA_Cout : out STD_LOGIC
        );
    end component;

begin
    temp_B <= not B when Cin = '1' else B;
    carries(N) <= Cin;

    ForGenerate: for i in (N-1) downto 0 generate
        UX: FullAdder port map(
            A(i),
            temp_B(i),
            carries(i+1),
            S(i),
            carries(i)
        );
    end generate ForGenerate;
    Cout <= carries(0);
end Behavior;

展望未来：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LookAheadAdder is
    Port ( 
        LAA_A    : in  STD_LOGIC;
        LAA_B    : in  STD_LOGIC;
        LAA_Cin  : in  STD_LOGIC;
        LAA_S    : out STD_LOGIC;
        LAA_Cout : out STD_LOGIC
    );
end LookAheadAdder;

architecture Behavior of LookAheadAdder is 
    signal P : STD_LOGIC;
    signal G : STD_LOGIC;
begin
    P       <= LAA_A xor LAA_B;
    G       <= LAA_A and LAA_B;
    LAA_S    <= P    xor LAA_Cin;
    LAA_Cout <= G or (P and LAA_Cin);
end Behavior;

相同的 N 位块，只是更改了组件：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LookAheadNBitsAdder is

    Generic( N : integer  := 8 );

    Port ( 
        A    : in  STD_LOGIC_VECTOR(0 to N-1);
        B    : in  STD_LOGIC_VECTOR(0 to N-1);
        Cin  : in  STD_LOGIC;
        S    : out STD_LOGIC_VECTOR(0 to N-1);
        Cout : out STD_LOGIC
    );

end LookAheadNBitsAdder;

architecture Behavior of LookAheadNBitsAdder is
    signal temp_B     : STD_LOGIC_VECTOR(0 to N-1);
    signal carries    : STD_LOGIC_VECTOR(0 to N);

    component LookAheadAdder Port(
            LAA_A    : in  STD_LOGIC;
            LAA_B    : in  STD_LOGIC;
            LAA_Cin  : in  STD_LOGIC;
            LAA_S    : out STD_LOGIC;
            LAA_Cout : out STD_LOGIC
        );
    end component;

begin
    temp_B <= not B when Cin = '1' else B;
    carries(N) <= Cin;

    ForGenerate: for i in (N-1) downto 0 generate
        UX: LookAheadAdder port map(
            A(i),
            temp_B(i),
            carries(i+1),
            S(i),
            carries(i)
        );
    end generate ForGenerate;
    Cout <= carries(0);
end Behavior;

我怎样才能更快地进行测试？我没有 FPGA，我可以用 ModelSim 做吗？我试过模拟，但看起来传播没有任何延迟，波只是从一个状态跳到另一个状态。

Answer 1

这两个都是写成组合逻辑的。这意味着输入将立即传播到输出。查看哪个是 "faster" 的唯一方法是引入一个时钟并开始计算时钟周期。您可以看到哪个会使用更少的芯片资源，但如果它们都是用组合逻辑（不是顺序的）编写的，那么在模拟中输出将是即时的。

这是一个前瞻加法器吗？以及如何对其进行基准测试？

Is this a look ahead adder? And how to benchmark it?

benchmarking

vhdl