(vhdl) 预期类型 = 当前类型类型错误

Question

我不断收到一条错误消息：

line 25: type error near num_values ; current type unsigned; expected type unsigned.

它已经是应该的类型了，我认为它的位长相同并且声明正确，我在这里做错了什么？

代码是关于fifo队列结构的实现。

<Queue.vhd>


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Queue is
    port (
        -- clock
        clk: in std_logic;
        -- input
        push: in std_logic;
        push_data: in std_logic_vector(31 downto 0);
        pop: in std_logic;
        -- output
        pop_data: out std_logic_vector(31 downto 0);
        num_values: out unsigned(31 downto 0)
    );
end entity;

architecture Behavioral of Queue is

type items is array(0 to 31) of std_logic_vector(31 downto 0);
signal manager : items := (others => (others => '0'));
signal push_idx, pop_idx : integer := 0;

begin
process(clk) is
variable howmany : integer := 0;


begin
if rising_edge(clk) then
    if (push = '1') then
        manager(push_idx) <= push_data;
        push_idx <= push_idx + 1;
        howmany := howmany + 1;
     end if;

     if (pop = '1') then
        if (howmany /= 0) then 
            pop_data <= manager(pop_idx);
            pop_idx <= pop_idx + 1;
            howmany := howmany - 1;
        end if;
        else
            pop_data <= std_logic_vector(to_unsigned(0,pop_data'length));
     end if;

     if (push_idx = 31) then
        push_idx <= 0;
     end if;

     if (pop_idx = 31) then
        pop_idx <= 0;
     end if;
num_values <= to_unsigned(howmany,32);
end if;
end process;
end architecture;

<QueueTb.vhd>

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity QueueTb is
end entity;

architecture sim of QueueTb is

    constant ClockFrequency : integer := 100e6;
    constant ClockPeriod : time := 1000ms / ClockFrequency;

    signal clk : std_logic := '0';
    signal push, pop : std_logic := '0';
    signal num_values : unsigned(31 downto 0);
    signal push_data, pop_data : std_logic_vector(31 downto 0) := (others =>'0');

begin

    UUT : entity work.Queue(Behavioral)
    port map(
        clk => clk,
        push   => push,
        pop   => pop,
        num_values  => num_values,    <=== this is where error occurs!
        push_data => push_data,
        pop_data => pop_data);

    clk <= not clk after ClockPeriod / 2;

    process is 
    begin
    wait for 10 ns;
    push <= '1';
    push_data <= conv_std_logic_vector(123,32);

    wait for 10 ns;
    push_data <= conv_std_logic_vector(456,32);

    wait for 10 ns;
    push <= '0';
    push_data <= conv_std_logic_vector(0,32);
    pop <= '1';

    wait for 10 ns;
    pop <= '0';
    push <= '1';
    push_data <= conv_std_logic_vector(789,32);

    wait for 10 ns;
    push <= '0';
    pop <= '1';
    wait for 80 ns;

    end process;
end architecture;

我哪里做错了？？

Answer 1

在 Queue 实体中您使用 ieee.numeric_std 并且在 QueueTB 中您使用 ieee.std_logic_arith 。两者都定义了不同的无符号类型。从测试平台中删除 std_logic_arith，因为它不是标准的 VHDL 库，而是使用 numeric_std。

(vhdl) 预期类型 = 当前类型类型错误

(vhdl) expected type = current type type error

queue

vhdl