有没有办法在 vhdl 的 case 语句中创建一个循环？

Question

我想知道是否有办法在 vhdl 中的 case 语句中创建循环。

目前我有这个代码

    CASE A1 IS 
        WHEN "00000" => RD1 <= REG0;
        WHEN "00001" => RD1 <= REG1;
        WHEN "00010" => RD1 <= REG2;
        WHEN "00011" => RD1 <= REG3;
        WHEN "00100" => RD1 <= REG4;
        WHEN "00101" => RD1 <= REG5;
        WHEN "00110" => RD1 <= REG6;
        WHEN "00111" => RD1 <= REG7;
        WHEN "01000" => RD1 <= REG8;
        WHEN "01001" => RD1 <= REG9;
        WHEN "01010" => RD1 <= REG10;
        WHEN "01011" => RD1 <= REG11;
        WHEN "01100" => RD1 <= REG12;
        WHEN "01101" => RD1 <= REG13;
        WHEN "01110" => RD1 <= REG14;
        WHEN "01111" => RD1 <= REG15;
        WHEN "10000" => RD1 <= REG16;
        WHEN "10001" => RD1 <= REG17;
        WHEN "10010" => RD1 <= REG18;
        WHEN "10011" => RD1 <= REG19;
        WHEN "10100" => RD1 <= REG20;
        WHEN "10101" => RD1 <= REG21;
        WHEN "10110" => RD1 <= REG22;
        WHEN "10111" => RD1 <= REG23;
        WHEN "11000" => RD1 <= REG24;
        WHEN "11001" => RD1 <= REG25;
        WHEN "11010" => RD1 <= REG26;
        WHEN "11011" => RD1 <= REG27;
        WHEN "11100" => RD1 <= REG28;
        WHEN "11101" => RD1 <= REG29;
        WHEN "11110" => RD1 <= REGZLO;
        WHEN "11111" => RD1 <= REGZHI;
        WHEN OTHERS => RD1 <= (OTHERS => '0');
     END CASE;

如您所见，从一个语句到下一个语句的唯一变化是分配给 RD1 的 REG 编号。难道它总是匹配 A1 的值（除了最后两种情况，但可以单独完成）这一事实是否可以用来制作一个循环，以便不必编写所有语句？

谢谢。

Answer 1

Is there a way to create a loop inside a case statement

不，你不能，至少不能以我认为你想要的方式去做。

这没有意义，因为如果可以使用循环，则可以将循环变量用作 selector/index，或者可以从中导出值。

A case 用于非常规 and/or 稀疏选择。

你当然可以在这样的情况下放置一个循环：

WHEN "01100" => for ...

但我很确定那不是你所指的。

Answer 2

-- Why have 30 different signals when 1 will do?
type reg_a is array(0 to 29) of std_logic_vector(?? downto 0);
signal reg_s : reg_a;

-- Don't use a loop when you can just index into an array
if (unsigned(A1) < 30) then
    RD1 <= reg_s(TO_INTEGER(unsigned(A1)));
else if (A1 = "11110") then
    RD1 <= REGZLO;
else
   RD1 <= REGZHI;
end if;

有没有办法在 vhdl 的 case 语句中创建一个循环？

Is there a way to create a loop inside a case statement on vhdl?

vhdl