VHDL：Case 语句选择必须涵盖所有可能的表达式值

Question

我正在做一个项目，该项目应该使用近似值将数据从模拟转换为数字，当我尝试在 Quartus II 9.1sp2 网络版中编译代码时出现错误，在下面的代码中以 Case Statement 的标题显示：

architecture behavior of adc is
type state is (reset, state1, state2, state3, state4, state5, state6, state7, state8, state9, state10);
signal nx_state : state;

begin
    process (in_clk, rst_n, start)
begin
    if(rst_n'event and rst_n='0') then
        B_hold <= "1111";
        D_out <= "0000";
        data_out <= "0000";
        hold <= '1';
        sample <= '0';
        eoc <= '0';
        
        if start = '1' then
            nx_state <= state1;
        else
            nx_state <= reset;
        end if;

    elsif(in_clk'event and in_clk='1') then
        case nx_state is
            when state1 => nx_state <= state2;
                B_hold <= "0000";
                hold <= '0';
                sample <= '1';
            
            when state2 => nx_state <= state3;
                B_hold <= "1111";
                D_out <= "0000";
            
            when state3 => nx_state <= state4;
                B_hold(3) <= '0';
                D_out(3) <= '1';
                data_out(3) <= '1';
            
            when state4 => nx_state <= state5;
                if comp_in = '1' then
                    B_hold(3) <= '0';
                    D_out(3) <= '1';
                    data_out(3) <= '1';
                else
                    B_hold(3) <= '1';
                    D_out(3) <= '0';
                    data_out(3) <= '0';
                end if;
            
            when state5 => nx_state <= state6;
                B_hold(2) <= '0';
                D_out(2) <= '1';
                data_out(2) <= '1';
            
            when state6 => nx_state <= state7;
                if comp_in = '1' then
                    B_hold(2) <= '0';
                    D_out(2) <= '1';
                    data_out(2) <= '1';
                else
                    B_hold(2) <= '1';
                    D_out(2) <= '0';
                    data_out(2) <= '0';
                end if;
            
            when state7 => nx_state <= state8;
                B_hold(1) <= '0';
                D_out(1) <= '1';
                data_out(1) <= '1';
            
            when state8 => nx_state <= state9; 
                if comp_in = '1' then
                    B_hold(1) <= '0';
                    D_out(1) <= '1';
                    data_out(1) <= '1';
                else
                    B_hold(1) <= '1';
                    D_out(1) <= '0';
                    data_out(1) <= '0';
                end if;
                
            when state9 => nx_state <= state10; 
                B_hold(0) <= '0';
                D_out(0) <= '1';
                data_out(0) <= '1';
            
            when state10 => nx_state <= reset;
                if comp_in = '1' then
                    B_hold(0) <= '0';
                    D_out(0) <= '1';
                    data_out(0) <= '1';
                else
                    B_hold(0) <= '1';
                    D_out(0) <= '0';
                    data_out(0) <= '0';
                end if;
                eoc <= '1';
        end case;
    end if;
end process;
end behavior;

我是 vhdl 的新手，我不知道上面显示的情况到底出了什么问题。

Answer 1

重置是电平敏感的。所以改变

if(rst_n'event and rst_n='0') then

到

if(rst_n='0') then

重置条件内有条件也很不正常

    if start = '1' then
        nx_state <= state1;
    else
        nx_state <= reset;
    end if;

因此，您可能只想：

    nx_state <= reset;

Answer 2

您的类型包含一个名为 reset 的状态。你需要那个状态的时间。

case nx_state is
    when reset =>

VHDL：Case 语句选择必须涵盖所有可能的表达式值

VHDL: Case Statement choices must cover all possible values of expression

vhdl