在 VHDL 中使用 SHIFTING 进行除法和乘法

Question

如何在 VHDL 中手动实现除法和乘法？那是;使用 Left & Right Shift 并且不需要 numeric_std（如果可能的话）。

Answer 1

可能的解决方案：

library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Shifter is
  generic(
            num_length : integer := 32
         ); 
    port(
            EN      : in std_logic;
            clk     : in std_logic;
            number  : in std_logic_vector((num_length - 1) downto 0);
            dir     : in std_logic;
            result  : out std_logic_vector((num_length - 1) downto 0));
end Shifter;
    
architecture Beh of Shifter is
    signal temp : std_logic_vector((num_length - 1) downto 0);
 begin
 
    result <= std_logic_vector(temp);
 
    process(EN, clk) is
    begin  
        if EN = '0' then
            temp <= (OTHERS => '0');
        elsif rising_edge(clk) then
            case dir is
                when '0' =>   temp <= '0' & number((num_length - 2) downto 0);
                when '1' =>   temp <= number((num_length - 2) downto 0) & '0';
            end case;
        end if;
    end process;
end Beh;

Every clk cycle the position increases/decreases (depends on dir setting)

也可以循环释放，这样模块一个周期可以increase/decrease多一个bit

Important: It is only possible to increase/decrease by the power of 2 (2,4,8,16,32,...) with shifting

在 VHDL 中使用 SHIFTING 进行除法和乘法

Devision and Multiplication using SHIFTING in VHDL

fpga

vhdl