Verilog多路复用器

Question

帮我解决这个问题，下面的问题

创建一个 16 位宽的 9 对 1 多路复用器。 sel=0 选择 a，sel=1 选择 b，等等。对于未使用的情况（sel=9 到 15），将所有输出位设置为“1”。

解决方案：

module top_module( 
input [15:0] a,b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always@(*) begin
    case(sel)
        0:
            out = a;
        1:
            out = b;
        2:
            out = c;
        3:
            out = d;
        4:
            out = e;
        5:
            out = f;
        6:
            out = g;
        7:
            out = h;
        8:
            out = i;
          
        default:
            out = 1;
       
    endcase
end

结束模块

我不知道这段代码有什么问题。可能是全部。

注：https://hdlbits.01xz.net/wiki/Mux9to1v

Answer 1

您没有 endomdule 关键字（意外的文件结尾）。
Always block require reg (procedural assignment to a non-register out)。不管是同步还是异步always块。

module top_module( 
    input [15:0] a,b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output reg [15:0] out
);

    always @(*) begin
        case(sel)
            0: out = a;
            1: out = b;
            2: out = c;
            3: out = d;
            4: out = e;
            5: out = f;
            6: out = g;
            7: out = h;
            8: out = i;
            default: out = 1;
        endcase
    end

endmodule

Answer 2

还是谢谢你。找到了答案。必须用 '1.

将所有输出位填充为 1

module top_module( 
input [15:0] a,b, c, d, e, f, g, h, i,
input [3:0] sel,
output reg [15:0] out
);
always @(*) begin
    case(sel)
        0: out = a;
        1: out = b;
        2: out = c;
        3: out = d;
        4: out = e;
        5: out = f;
        6: out = g;
        7: out = h;
        8: out = i;
        default: out = '1;
    endcase
end

结束模块

Answer 3

module top_module( 
input [15:0] a,b, c, d, e, f, g, h, i,
input [3:0] sel,
output reg [15:0] out
);
always @(*) begin
    case(sel)
        0: out = a;
        1: out = b;
        2: out = c;
        3: out = d;
        4: out = e;
        5: out = f;
        6: out = g;
        7: out = h;
        8: out = i;
        default: out = {16{1'b1}}; //..'1 is not the same in every compiler
    endcase
end
endmodule

Verilog多路复用器

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