当计数器达到两个特定值时如何获得 outputs/pulses？

Question

我创建了一个计数到 30 的计数器。我有一个输出信号 out。在两个特定的计数下，即当计数器达到 10 (first) 和当计数器达到 15 (second) 时，我希望输出变低。不知何故，我在这里缺少一个基本逻辑，因为只有在一个特定的计数（10 或 15）时，我才能使输出为零。

这是代码

module user_def_pulse(
    output integer counter,
    output reg out,
    input clk, reset
    );

    parameter no_of_counts = 30;
    parameter first = 10;
    parameter second = 15;
 
    initial
    begin
        counter = 0;
        out = 1'b0;
    end
        
    always @(posedge clk)
        begin
            if (reset)
            begin
                counter <= 1'b0;
            end
            else if (counter == no_of_counts)
            begin
                counter <= 1'b0;
                out <= 1'b0;
            end
            else
            begin
                if ((counter == first) || (counter == second))
                    out <= 1'b0;
                else
                    begin
                    counter <= counter + 1;
                    out <= 1'b1;
                    $display($time," The value of counter is %d", counter);
                    end
            end
        end
endmodule

这里是测试台

module user_def_pulse_tb(
);
    parameter time_period = 10;
    
    wire [31:0] COUNTER;
    wire OUT;
    reg CLK, RESET;
    
    user_def_pulse udp1 (.counter(COUNTER), .out(OUT),  .clk(CLK), .reset(RESET));
      
    initial
        begin
            CLK = 1'b0;
            RESET = 1'b1;
            #20 RESET = 1'b0;
        end
    
    always
        #time_period CLK = ~CLK;
  
endmodule

这是输出波形。

Answer 1

您的代码存在的问题是一旦达到 first 值就停止递增计数器。您需要不断增加计数器。我将增量移到了 if ((counter == first) || ... 子句之外。

always @(posedge clk) begin
    if (reset) begin
        counter <= 1'b0;
    end else if (counter == no_of_counts) begin
        counter <= 1'b0;
        out <= 1'b0;
    end else begin
        counter <= counter + 1;
        $display($time," The value of counter is %d", counter);
        if ((counter == first) || (counter == second)) begin
            out <= 1'b0;
        end else begin
            out <= 1'b1;
        end
    end
end

当计数器达到两个特定值时如何获得 outputs/pulses？

How to get outputs/pulses when counter reaches two particular values?

verilog

system-verilog