将索引转换为值的模块：文本“=”附近的语法错误；期待“。”或“（”

Question

这个模块应该将索引值iState转换为数组sequence和return中对应的值oV。但是，当我运行时，我在 oV = sequence[iState]; 收到此错误：

Error (10170): Verilog HDL syntax error at assign32498071.v(70) near text "="; expecting ".", or "("

module StateToCountSequence(iState, oV);
    //declare the input and output 
    input iState;
    output [3:0]oV;
  
    //declare any internal wire and reg types here.
    reg [3:0]sequence[14:0];
    
    initial begin
        sequence[0] = 4'd3;
        sequence[1] = 4'd2;
        sequence[2] = 4'd4;
        sequence[3] = 4'd9;
        sequence[4] = 4'd9;
        sequence[5] = 4'd0;
        sequence[6] = 4'd7;
        sequence[7] = 4'd1;
        sequence[8] = 4'd1;
        sequence[9] = 4'd5;
        sequence[10] = 4'd1;
        sequence[11] = 4'd7;
        sequence[12] = 4'd0;
        sequence[13] = 4'd8;
        sequence[14] = 4'd9;
    end

    oV = sequence[iState];
endmodule

有人知道我应该怎么做吗？

Answer 1

您缺少 assign 关键字来连续分配给 oV。变化：

oV = sequence[iState];

至：

assign oV = sequence[iState];

修复了编译错误。

很奇怪你的索引信号(iState)是一个1位信号，也就是说它只能取已知值0和1。因此，你只能访问sequence [0] 和 [1].

请注意，sequence 是一个 SystemVerilog 关键字，这意味着如果您的工具启用了 SV 功能，则它不能用作信号名称。我建议将名称更改为其他名称。

将索引转换为值的模块：文本“=”附近的语法错误；期待“。”或“（”

Module that converts index to a value: syntax error near text "="; expecting ".", or "("

verilog