VHDL 输入输出端口设置为高阻抗

Question

更新

我更新了测试台代码，但现在，数据缓冲区似乎无法驱动信号。

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY databus_buffer_tb IS
END databus_buffer_tb;


ARCHITECTURE dataflow OF databus_buffer_tb IS
  SIGNAL T_Idata:STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL T_Odata:STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL T_Ctrl:STD_LOGIC:='0';
  COMPONENT databus_buffer IS
      PORT
         (
           --IDATA represent the bus lines that comes from the uC for reading and writing;
           --ODATA represents the bus lines that communicate with the internal bus;
           IDATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
           CTRL:     IN      STD_LOGIC;
           ODATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000"
     );
   END COMPONENT;

BEGIN
  databuffer:databus_buffer PORT MAP
    (
      IDATA=>T_Idata,
      CTRL=>T_Ctrl,
      ODATA=>T_Odata
      );
  PROCESS
  BEGIN



    T_Idata<="00001111";

    T_Ctrl<='0';
    WAIT FOR 10 ns;
    assert(T_Odata="00001111") REPORT "Expected 00001111" SEVERITY error;

    T_Odata<="11110000";

    T_Ctrl<='1';
    WAIT FOR 10 ns;
    assert(T_Idata="11110000") REPORT "Expected 11110000" SEVERITY error;


    T_Ctrl<='Z';
    WAIT FOR 10 ns;
    assert(T_Idata="ZZZZZZZZ") REPORT "Expected Z FOR T_Idata" SEVERITY error;
    assert(T_Odata="ZZZZZZZZ") REPORT "Expected Z FOR T_Odata" SEVERITY error;
    wait;
  END PROCESS;
END dataflow;

和

我试图了解应该如何在 VHDL 中实现 INOUT 端口，但我失败了。这是代码：

    library ieee;
use ieee.std_logic_1164.all;
----------------------------
-- Databus Buffer
----------------------------
ENTITY databus_buffer IS
-- data bus buffer have the next ports:
-- IDATA:        8 bit bus       ->inout
-- CTRL:        1 bit control   ->in
-- ODATA:       8 bit bus       ->inout
    PORT
    (
        --IDATA represent the bus lines that comes from the uC for reading and writing;
        --ODATA represents the bus lines that communicate with the internal bus;
            IDATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
            CTRL:     IN      STD_LOGIC;
            ODATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0)
        );



END databus_buffer;
ARCHITECTURE behaviour OF databus_buffer IS
-- behaviour of databus buffer;

BEGIN
-- is a 3 state bidirection 8 bit buffer.
-- if CTRL is 1, IDATA=ODATA; reading from counter operation
-- if CTRL is 0, ODATA=IDATA; writing to control word
-- if CTRL is Z, IDATA=Z; this happens when nor read and write are active but
-- cs is active;
-- also, data bus can be in 3rd state if the chip is not selected, this means
-- that CTRL will be Z;


    ODATA<=IDATA WHEN CTRL='0' else "ZZZZZZZZ" WHEN CTRL='Z' else (OTHERS=>'Z');
    IDATA<=ODATA WHEN CTRL='1' else "ZZZZZZZZ" WHEN CTRL='Z' else (OTHERS=>'Z');



END behaviour;

此代码在CTRL为0或1时有效。但是当我将CTRL设置为'Z'时，在高阻状态下，IDATA和ODATA并未设置为高阻状态。

我的测试平台：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY databus_buffer_tb IS
END databus_buffer_tb;


ARCHITECTURE dataflow OF databus_buffer_tb IS
  SIGNAL T_Idata:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
  SIGNAL T_Odata:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
  SIGNAL T_Ctrl:STD_LOGIC:='0';
  COMPONENT databus_buffer IS
      PORT
         (
           --IDATA represent the bus lines that comes from the uC for reading and writing;
           --ODATA represents the bus lines that communicate with the internal bus;
           IDATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
           CTRL:     IN      STD_LOGIC;
           ODATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0)
     );
   END COMPONENT;

BEGIN
  databuffer:databus_buffer PORT MAP
    (
      IDATA=>T_Idata,
      CTRL=>T_Ctrl,
      ODATA=>T_Odata
      );
  PROCESS
  BEGIN
    T_Idata<="00000000";
    T_Odata<="00000000";
    T_Ctrl<='0';

    T_Idata<="00001111";
    T_ODATA<="ZZZZZZZZ";
    T_Ctrl<='0';
    WAIT FOR 10 ns;
    assert(T_Odata="00001111") REPORT "Expected 00001111" SEVERITY error;

    T_Odata<="11110000";
    T_IDATA<="ZZZZZZZZ";
    T_Ctrl<='1';
    WAIT FOR 10 ns;
    assert(T_Idata="11110000") REPORT "Expected 11110000" SEVERITY error;

    T_IData<="00000000";
    T_OData<="00000000";    
    T_Ctrl<='Z';
    WAIT FOR 10 ns;
    assert(T_Idata="ZZZZZZZZ") REPORT "Expected Z FOR T_Idata" SEVERITY error;
    assert(T_Odata="ZZZZZZZZ") REPORT "Expected Z FOR T_Odata" SEVERITY error;
    wait;
  END PROCESS;
END dataflow;

此外，如何按顺序控制进程中的输入输出端口？

Answer 1

您有多个 T_IDATA 和 T_ODATA 的驱动程序。这些信号由测试平台和数据缓冲区驱动。最终结果由std_logic的解析函数决定。在最后一个（非工作）案例中，测试台本身将 T_IDATA 和 T_ODATA 驱动到低电平。

让我们看一个有效的案例：（取自原始测试台的示例，此案例在更新的测试台中被破坏，因为信号 T_ODATA 没有初始化。）

T_Idata<="00001111";
T_ODATA<="ZZZZZZZZ";
T_Ctrl<='0';
WAIT FOR 10 ns;
assert(T_Odata="00001111") REPORT "Expected 00001111" SEVERITY error;

此处，测试台驱动 T_ODATA <= "ZZZZZZZZ" 和数据缓冲区 T_ODATA <= "00001111"。这被解析为“00001111”，因此断言得到满足。

现在不行的情况：

T_IData<="00000000";
T_OData<="00000000";    
T_Ctrl<='Z';
WAIT FOR 10 ns;
assert(T_Idata="ZZZZZZZZ") REPORT "Expected Z FOR T_Idata" SEVERITY error;
assert(T_Odata="ZZZZZZZZ") REPORT "Expected Z FOR T_Odata" SEVERITY error;

此处，测试台驱动 T_ODATA <= "00000000" 和数据缓冲区 T_ODATA <= "ZZZZZZZZ"。这被解析为“00000000”，因此断言失败。同样适用于 T_IDATA.

编辑：在这种非工作情况下，测试台也应该驱动

T_IData<="ZZZZZZZZ";
T_OData<="ZZZZZZZZ";

得到预期的结果。

编辑 2：这些行必须添加到更新的测试台中，否则测试台中的先前分配将用于解析。

VHDL 输入输出端口设置为高阻抗

VHDL inout port set to high impedance

vhdl