vhdl 减去 std_logic_vector
vhdl subtract std_logic_vector
我正在尝试减去 2 个标准逻辑向量并得到错误
p2 <= p1(11 downto 0)- idata(11 downto 0);
Error (10327): VHDL error at sub.vhd(32): can't determine definition of operator ""-"" -- found 0 possible definitions
我已经尝试添加 use IEEE.std_logic_signed.all
或 use IEEE.std_logic_unsigned.all
或两者并且已经尝试过
p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use IEEE.std_logic_signed.all;
--use IEEE.std_logic_unsigned.all;
entity sub is
port (
clk : in std_logic;
rst : in std_logic;
--en : in std_logic;
idata : in std_logic_vector (11 downto 0);
odata : out std_logic_vector (11 downto 0)
);
end sub;
architecture beh of sub is
signal p1,p2 :std_logic_vector (11 downto 0);
begin
process (clk, rst)
begin
if (rst = '1') then
odata <= "000000000000";
elsif (rising_edge (clk)) then
p1 <= idata;
p2 <= p1(11 downto 0)- idata(11 downto 0);
--p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));
end if;
end process;
odata<=p2;
end beh;
std_logic_vector
类型只是 std_logic
的数组,本身没有任何数值解释,因此在尝试应用减号 (-
).
不要使用 Synopsys 非标准 std_logic_signed/unsigned/arith
包。
VHDL-2002:使用标准ieee.numeric_std
包中的unsigned
类型将std_logic_vector
转换为unsigned
表示,它允许使用减号等数字运算。代码如下:
use ieee.numeric_std.all;
...
p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));
VHDL-2008:使用标准 ieee.numeric_std_unsigned
包将 std_logic_vector
转换为 unsigned
表示,这允许使用数字减号之类的操作。代码如下:
use ieee.numeric_std_unsigned.all;
...
p2 <= p1(11 downto 0) - idata(11 downto 0);
顺便说一句。查看此 search 以了解类似问题。
我正在尝试减去 2 个标准逻辑向量并得到错误
p2 <= p1(11 downto 0)- idata(11 downto 0);
Error (10327): VHDL error at sub.vhd(32): can't determine definition of operator ""-"" -- found 0 possible definitions
我已经尝试添加 use IEEE.std_logic_signed.all
或 use IEEE.std_logic_unsigned.all
或两者并且已经尝试过
p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use IEEE.std_logic_signed.all;
--use IEEE.std_logic_unsigned.all;
entity sub is
port (
clk : in std_logic;
rst : in std_logic;
--en : in std_logic;
idata : in std_logic_vector (11 downto 0);
odata : out std_logic_vector (11 downto 0)
);
end sub;
architecture beh of sub is
signal p1,p2 :std_logic_vector (11 downto 0);
begin
process (clk, rst)
begin
if (rst = '1') then
odata <= "000000000000";
elsif (rising_edge (clk)) then
p1 <= idata;
p2 <= p1(11 downto 0)- idata(11 downto 0);
--p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));
end if;
end process;
odata<=p2;
end beh;
std_logic_vector
类型只是 std_logic
的数组,本身没有任何数值解释,因此在尝试应用减号 (-
).
不要使用 Synopsys 非标准 std_logic_signed/unsigned/arith
包。
VHDL-2002:使用标准ieee.numeric_std
包中的unsigned
类型将std_logic_vector
转换为unsigned
表示,它允许使用减号等数字运算。代码如下:
use ieee.numeric_std.all;
...
p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));
VHDL-2008:使用标准 ieee.numeric_std_unsigned
包将 std_logic_vector
转换为 unsigned
表示,这允许使用数字减号之类的操作。代码如下:
use ieee.numeric_std_unsigned.all;
...
p2 <= p1(11 downto 0) - idata(11 downto 0);
顺便说一句。查看此 search 以了解类似问题。