Error: VHDL compiler exiting

Question

我正在使用 modelsim。我写了简单的代码，但出现错误。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



entity clk_counter is
port(output    : out   bit;
     clk : in bit
   );
end clk_counter;

architecture rtl of clk_counter_arch is

    signal clock_counter_output_flag: bit;
    constant clock_max_count : integer := 20000;


begin

     process (clock_counter_output_flag, clk,CLK'event )

       variable clock_count : integer := 0; 
       --constant clock_max_count : integer := 20000;
       variable clock_out : bit := 0;
       -- wait until CLK'event and CLK='1';
          begin
              if (CLK'event and CLK='1') then
                  clock_count := clock_count+1;
                  if (clock_count = clock_max_count) then
                      clock_out := 1;
                   else
                       clock_out := 0;  
                  end if
               end if
               clock_counter_output_flag <= clock_out;        
          end process;


END Architecture;

错误信息：

 # ** Error: (vcom-11) Could not find work.clk_counter_arch.                    
 #                                                                         
 # ** Error: C:/Modeltech_pe_edu_10.4a/examples/work/src/clk_counter(13):              VHDL Compiler exiting

Answer 1

您的实体名称是 clk_counter 并且您定义了 clk_counter_arch 的架构 rtl。因此，您遇到了错误。将 clk_counter_arch 更改为 clk_counter.

其次，您应该像结束 rtl 一样结束架构。

此外，您为什么要使用两个额外的变量 clock_out 和 clock_counter_output_flag？如果你想把这些值作为代码的输出，你应该简单地写

if (CLK'event and CLK='1') then
                  clock_count := clock_count+1;
                  if (clock_count = clock_max_count) then
                      output<='1';
                   else
                       output <='0';  
                  end if;
               end if;

Error: VHDL compiler exiting

Error: VHDL compiler exiting

vhdl