半加器和全加器逻辑?
Half Adder and Full Adder logic?
我无法通过半加器和全加器测试,我想知道我在 FullAdder()
和 HalfAdder()
方法中的逻辑有什么问题? None 我的测试似乎由于某种原因通过了...
代码如下:
# All wires that enter/exit the circuit need to be visible outside of the
# function: they are to be created in the enclosing scope and passed
# as parameters.
# However, wires that connect the AND gates to the OR gates are
# _internal wires_, visible only inside the circuit: they need to be created
xy = self.Wire('xy')
xz = self.Wire('xz')
yz = self.Wire('yz')
xy_or_xz = self.Wire('xy_or_xz')
self.AndGate(x, y, xy)
self.AndGate(x, z, xz)
self.Andgate(x, z, yz)
# OR(xy,xz,yz) = OR( OR(xy,xz), yz)
self.OrGate(xy, xz, xy_or_xz)
self.OrGate(xy_or_xz, yz, o)
return 'ok'
def TwoSwitches(self, x, y, o):
""" An example: light controlled by 2 switches (Rosen, 12.3, Example 3,
- Figure 6, p. 825)
F(x, y) = xy + !x.!y
"""
# Wires x, y, and o are passed as parameters.
# Only the internal wires need to be created:
xy = self.Wire('xy')
not_x = self.Wire('not_x')
not_y = self.Wire('not_y')
notx_noty = self.Wire('notx_noty')
self.AndGate(x,y,xy)
self.Inverter(x, not_x)
self.Inverter(y, not_y)
self.AndGate(not_x, not_y, notx_noty)
self.OrGate(xy, notx_noty, o)
return 'ok'
# This function needs to be defined: parameter, body definition
def HalfAdder(self, x, y, s, c):
notx_and_y=self.wire('notx_and_y')
x_and_noty=self.wire('x_and_noty')
cwire=self.wire('cwire')
allwire=self.wire(allwire)
self.OrGate(self.AndGate(not x,y,notx_and_y),self.AndGate(x,not y,x_and_noty),allwire)
cwire=self.AndGate(x,y,cwire)
c=cwire
s=allwire
pass
def FullAdder(self,x,y,c_i,s, c_out):
#TODO
pass
半加器
可以使用与门和异或门实现半加器:
x y
| |
|------------------\
| |--------\ |
+--------+ +--------+
| AND | | XOR |
+--------+ +--------+
| |
c s
所以实现是这样的:
def Xor(self, x, y, xor):
nx = self.Wire('nx')
ny = self.Wire('ny')
self.Inverter(x,nx)
self.Inverter(x,ny)
a1 = self.Wire('a1')
a2 = self.Wire('a2')
self.AndGate(nx,y,a1)
self.AndGate(x,ny,a2)
self.OrGate(a1,a2,xor)
pass
def HalfAdder(self, x, y, s, c):
self.AndGate(x,y,c)
self.Xor(x,y,s)
全加器
有几种构建 全加器的方法 ,一种方法是使用两个半加器,就像我在 digital electronics 上的课程文本中解释的那样(荷兰语,抱歉):
x y c_i
| | |
+--------+ |
/-| HA | |
| +--------+ |
| | |
| `---------\ |
| | |
| +--------+
| /--------| HA |
| | +--------+
+--------+ |
| OR | s
+--------+
|
c_out
在 HalfAdder
、x
和 y
的顶部,左侧是 c
,底部是 s
。
所以这意味着:
def FullAdder(self,x,y,c_i,s, c_out):
ha1s = self.Wire('ha1s')
ha1c = self.Wire('ha1c')
self.HalfAdder(x,y,ha1s,ha1c)
ha2c = self.Wire('ha2c')
self.HalfAdder(ha1s,c_i,s,ha2c)
self.OrGate(ha1c,ha2c,c_out)
pass
一条一般性建议是,始终将问题拆分为您可以更轻松控制的更小的子问题。
我无法通过半加器和全加器测试,我想知道我在 FullAdder()
和 HalfAdder()
方法中的逻辑有什么问题? None 我的测试似乎由于某种原因通过了...
代码如下:
# All wires that enter/exit the circuit need to be visible outside of the
# function: they are to be created in the enclosing scope and passed
# as parameters.
# However, wires that connect the AND gates to the OR gates are
# _internal wires_, visible only inside the circuit: they need to be created
xy = self.Wire('xy')
xz = self.Wire('xz')
yz = self.Wire('yz')
xy_or_xz = self.Wire('xy_or_xz')
self.AndGate(x, y, xy)
self.AndGate(x, z, xz)
self.Andgate(x, z, yz)
# OR(xy,xz,yz) = OR( OR(xy,xz), yz)
self.OrGate(xy, xz, xy_or_xz)
self.OrGate(xy_or_xz, yz, o)
return 'ok'
def TwoSwitches(self, x, y, o):
""" An example: light controlled by 2 switches (Rosen, 12.3, Example 3,
- Figure 6, p. 825)
F(x, y) = xy + !x.!y
"""
# Wires x, y, and o are passed as parameters.
# Only the internal wires need to be created:
xy = self.Wire('xy')
not_x = self.Wire('not_x')
not_y = self.Wire('not_y')
notx_noty = self.Wire('notx_noty')
self.AndGate(x,y,xy)
self.Inverter(x, not_x)
self.Inverter(y, not_y)
self.AndGate(not_x, not_y, notx_noty)
self.OrGate(xy, notx_noty, o)
return 'ok'
# This function needs to be defined: parameter, body definition
def HalfAdder(self, x, y, s, c):
notx_and_y=self.wire('notx_and_y')
x_and_noty=self.wire('x_and_noty')
cwire=self.wire('cwire')
allwire=self.wire(allwire)
self.OrGate(self.AndGate(not x,y,notx_and_y),self.AndGate(x,not y,x_and_noty),allwire)
cwire=self.AndGate(x,y,cwire)
c=cwire
s=allwire
pass
def FullAdder(self,x,y,c_i,s, c_out):
#TODO
pass
半加器
可以使用与门和异或门实现半加器:
x y
| |
|------------------\
| |--------\ |
+--------+ +--------+
| AND | | XOR |
+--------+ +--------+
| |
c s
所以实现是这样的:
def Xor(self, x, y, xor):
nx = self.Wire('nx')
ny = self.Wire('ny')
self.Inverter(x,nx)
self.Inverter(x,ny)
a1 = self.Wire('a1')
a2 = self.Wire('a2')
self.AndGate(nx,y,a1)
self.AndGate(x,ny,a2)
self.OrGate(a1,a2,xor)
pass
def HalfAdder(self, x, y, s, c):
self.AndGate(x,y,c)
self.Xor(x,y,s)
全加器
有几种构建 全加器的方法 ,一种方法是使用两个半加器,就像我在 digital electronics 上的课程文本中解释的那样(荷兰语,抱歉):
x y c_i
| | |
+--------+ |
/-| HA | |
| +--------+ |
| | |
| `---------\ |
| | |
| +--------+
| /--------| HA |
| | +--------+
+--------+ |
| OR | s
+--------+
|
c_out
在 HalfAdder
、x
和 y
的顶部,左侧是 c
,底部是 s
。
所以这意味着:
def FullAdder(self,x,y,c_i,s, c_out):
ha1s = self.Wire('ha1s')
ha1c = self.Wire('ha1c')
self.HalfAdder(x,y,ha1s,ha1c)
ha2c = self.Wire('ha2c')
self.HalfAdder(ha1s,c_i,s,ha2c)
self.OrGate(ha1c,ha2c,c_out)
pass
一条一般性建议是,始终将问题拆分为您可以更轻松控制的更小的子问题。