verilog-构建一个小型组合电路

Question

我想构建一个小型组合电路（几个或，1 和，1 不是门），我在测试台上偶然发现了一个问题（甚至可能之前），希望有人能帮助我。

这是代码：

module hewi(input D3,D2,D1,D0,output A0,A1,V);

  wire k,s; //outputs of the and and not gates
  not N01(k,D2);
  and An1(s,k,D1);
  or Ou1(A0,D3,s);
  or Ou2(A1,D3,D2);
  or Oufinal(V,D3,D2,D1,D0);
endmodule

这是测试平台代码

module test_benche();

  wire D3,D2,D1,D0,A0,A1,V;
  hewi test(D3,D2,D1,D0,A0,A1,V);

  initial 
  begin
    D3 = 1`b0;
    D2 = 1`b0;
    D1 = 1`b0;
    D0 = 1`b0;
    #50;
    D3=1`b1;
    D2=1`b0;
    D1=1`b1;
    D0=1`b1;
  end
endmodule

我收到的问题是它无法检查这些表达式中的任何一个：

Undefined macro exists as: 'b0'   
  "testbench.sv", 8: token is '`b0'
         D3=1`b0;
                ^

我在这里错过了什么？

Answer 1

语法错误是因为您使用的是反引号 (`) 而不是单引号 (')

All compiler directives are preceded by the (`) character. This character is called grave accent (ASCII 0x60). It is different from the character ('), which is the apostrophe character (ASCII 0x27). The scope of a compiler directive extends from the point where it is processed, across all files processed in the current compilation unit, to the point where another compiler directive supersedes it or the processing of the compilation unit completes. The semantics of compiler directives is defined in LRM Section 3.12.1 and 5.6.4.

Answer 2

关于以下错误：

Error-[IBLHS-NT] Illegal behavioral left hand side testbench.sv, 15 Net type cannot be used on the left side of this assignment. The offending expression is : D1 Source info: D1 = 1'b1

无法在 always 或 initial 块中分配电线。因此需要将它们转换为reg类型。

//Control signals reg type
reg  D3,D2,D1,D0;
//Outputs driven from DUT wires
wire A0,A1,V;
  hewi test(D3,D2,D1,D0,A0,A1,V);

  initial 
  begin
    D3 = 1'b0;
    D2 = 1'b0;
    D1 = 1'b0;
    D0 = 1'b0;
    #50;
    D3=1'b1;
    D2=1'b0;
    D1=1'b1;
    D0=1'b1;
  end
endmodule

verilog-构建一个小型组合电路

verilog- building a small combinational circuit

logic

verilog

test-bench