为什么 Xilinx ISE 不在状态机中接受此声明？

Question

所以我目前正在做一个涉及 hd44780 显示器的小项目。但是因为我想编写自己的初始化序列，所以我决定使用状态机。我对 FPGA 很陌生，他们的编程来自 Java 背景。

这是我的状态机块。

我说它有效，IDE 没有显示任何错误。

    always @(posedge reset)
    begin
    en_timeout <= 2'b00;
    timeout <= 14'b00000000000000;
    init <= 4'b000;
    data <= 8'b00000000;
    en <= 1'b1; //active low
    rs <= 1'b0;
    rw <= 1'b0;
    state <= 4'b0000;
    next_state <= 4'b0000;

    debug <= 1'b0;
    end

if(timeout == 0)
    begin //Begin of Initiation state machine
        case(state)
            s0:
                begin
                end

            s1:
                begin
                end
            s2:
                begin
                end
            s3:
                begin
                end
            s4:
                begin
                end
            s5:
                begin
                end
            s6:
                begin
                end
            s7:
                begin
                end
            s8:
                begin
                end
            s9:
                begin
                end
            s10:
                begin
                end
            normal:
                begin
                end
        endcase
    end //End of Initiation state machine

但是如果我在其中一个状态的开始和结束之间添加任何赋值，它会显示 "Line n: Syntax error near "<="."

例如：

            case(state)
            s0:
                begin
                state <= s1;
                end

到目前为止我的 DisplayDriver 的完整代码：

    module DisplayDriver(
    output reg [8:0] data,
     output reg en,
    output reg rs,
    output reg rw,
     output reg debug,
     input clk,
     input reset
    );

     parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,s9=9,s10=10,normal = 11;

     reg [3:0] state; // 4 bit for max 11 combinations s0-s10 and normal
     reg [3:0] state; // 4 bit for max 11 combinations s0-s10 and normal [next State]
     reg [1:0] en_timeout; // 2 bit for en high to low to high cylce
     reg [13:0] timeout; // 14 bit 

    initial 
    // begin init
        begin
        en_timeout <= 2'b00;
        timeout <= 14'b00000000000000;
        init <= 4'b000;
        data <= 8'b00000000;
        en <= 1'b1; //active low
        rs <= 1'b0;
        rw <= 1'b0;
        state <= 4'b0000;
        next_state <= 4'b0000;

        debug <= 1'b0;
        end
     // end of init

    always @(posedge clk)
    //begin of everything that needs the clock
    begin
        if(en_timeout > 0) //begin timeout stack
            begin
            en_timeout <= en_timeout -1;
            en <= ~en;// if en_timeout = 2 -> en = 0; if en_timeout = 1 -> en = 1;
            end
        else if (timeout > 0) timeout <= timeout -1; //end timeout stack

        if(timeout == 0)state <= next_state;
    end //end of everything that needs the clock


    always @(posedge reset)
        begin
        en_timeout <= 2'b00;
        timeout <= 14'b00000000000000;
        init <= 4'b000;
        data <= 8'b00000000;
        en <= 1'b1; //active low
        rs <= 1'b0;
        rw <= 1'b0;
        state <= 4'b0000;
        next_state <= 4'b0000;

        debug <= 1'b0;
        end

    if(timeout == 0)
        begin //Begin of Initiation state machine
            case(state)
                s0:
                    begin
                    end

                s1:
                    begin
                    end
                s2:
                    begin
                    end
                s3:
                    begin
                    end
                s4:
                    begin
                    end
                s5:
                    begin
                    end
                s6:
                    begin
                    end
                s7:
                    begin
                    end
                s8:
                    begin
                    end
                s9:
                    begin
                    end
                s10:
                    begin
                    end
                normal:
                    begin
                    end
            endcase
        end //End of Initiation state machine
endmodule

有谁知道它为什么会这样？

Answer 1

我假设您正在尝试为 "state" 合成一个寄存器，在这种情况下更新“<=”需要始终在内部（@posedge clk）。

为什么 Xilinx ISE 不在状态机中接受此声明？

Why wont Xilinx ISE accept this statement in a state machine?

verilog

fpga

xilinx-ise