无法在计数器 Verilog 中适应可设置性
Can't fit settability in counter Verilog
我已经编写了 up/down 计数器并为可设置的起点创建了代码。到目前为止一切顺利,但我想不出如何将它添加到柜台。我必须强调,我对 Verilog 和类似语言完全陌生。
//UTILS
reg [2:0] delay;
wire clock;
reg[3:0] tens;
reg[3:0] units;
wire[5:0] number;
reg[13:0] shift;
integer i;
//ASSIGNS
assign number[5:0] = SW[5:0];
assign up = SW[7];
assign start = SW[6];
//PRESCALER
always@ (posedge MCLK)
begin
delay <= delay + 1;
end
assign clock = &delay;
//MAIN COUNTER
always@ (posedge clock)
begin
if (start)
begin
if (up) //going up
begin
if (units == 4'd3 && tens == 4'd6)
begin //63 reached
units <= 0;
tens <=0;
end
if (units==4'd9)
begin //x9 reached
units <= 0;
tens <= tens + 1;
end
else
units <= units + 1; //typical case
end
else //goin down
begin
if (units == 4'd0)
if ( tens ==4'd0) //00 reached back to 63
begin
units <= 4'd3;
tens <= 4'd6;
end
else
begin //x0 reached
tens <= tens-1;
units <= 4'd9;
end
else
begin //typical case
units <= units -1;
end
end
end
end //MAIN COUNTER END
这里我不知道如何合并这两个部分,我很想这样
如果开始
always@posedge时钟
/计数/
别的
/* 几乎功能性地改变数字(当改变发生时立即)*/
将其添加到 if(start) else 中似乎可以完成工作,但仅在相当低频率时钟的上升沿上。据我所知,我不能在两个不同的 ALWAYS@ 中使用一个 reg。
/* // Clear previous number and store new number in shift register
shift[13:6] = 0;
shift[5:0] = number;
//BINARY TO BCD
for (i=0; i<6; i=i+1)
begin
if (shift[9:6] >= 5)
shift[9:6] = shift[9:6] + 3;
if (shift[13:10] >= 5)
shift[13:10] = shift[13:10] + 3;
shift = shift << 1;
end
units <= shift[9:6];
tens <= shift[13:10];
*/
dek7seg 是7段显示,100%正常(教授代码)。
dek7seg ss1(
.bits(units[3:0]),
.seg(DISP1[6:0])
);
dek7seg ss10(
.bits(tens[3:0]),
.seg(DISP2[6:0])
);
endmodule
您正在使用衍生时钟来控制您的主计数器。而是使用主时钟 MCLK
并使用 delay
的逻辑作为条件语句。
由于您希望在 number
发生变化时存储新值,因此您需要存储之前的 number
值并进行比较。
根据您的描述,您的代码应如下所示:
//MAIN COUNTER
always@ (posedge MCLK)
begin
if (start && &delay)
begin
/* your up/down logic here */
end
else if (number != prev_number)
begin // Clear previous number and store new number
prev_number <= number;
units <= new_units;
tens <= new_tens;
end
end
// Calculate new units and tens from number
always @* begin
shift[13:6] = 0;
shift[5:0] = number;
//BINARY TO BCD
for (i=0; i<6; i=i+1) begin
if (shift[9:6] >= 5)
shift[9:6] = shift[9:6] + 3;
if (shift[13:10] >= 5)
shift[13:10] = shift[13:10] + 3;
shift = shift << 1;
end
new_units = shift[9:6];
new_tens = shift[13:10];
end
我已经编写了 up/down 计数器并为可设置的起点创建了代码。到目前为止一切顺利,但我想不出如何将它添加到柜台。我必须强调,我对 Verilog 和类似语言完全陌生。
//UTILS
reg [2:0] delay;
wire clock;
reg[3:0] tens;
reg[3:0] units;
wire[5:0] number;
reg[13:0] shift;
integer i;
//ASSIGNS
assign number[5:0] = SW[5:0];
assign up = SW[7];
assign start = SW[6];
//PRESCALER
always@ (posedge MCLK)
begin
delay <= delay + 1;
end
assign clock = &delay;
//MAIN COUNTER
always@ (posedge clock)
begin
if (start)
begin
if (up) //going up
begin
if (units == 4'd3 && tens == 4'd6)
begin //63 reached
units <= 0;
tens <=0;
end
if (units==4'd9)
begin //x9 reached
units <= 0;
tens <= tens + 1;
end
else
units <= units + 1; //typical case
end
else //goin down
begin
if (units == 4'd0)
if ( tens ==4'd0) //00 reached back to 63
begin
units <= 4'd3;
tens <= 4'd6;
end
else
begin //x0 reached
tens <= tens-1;
units <= 4'd9;
end
else
begin //typical case
units <= units -1;
end
end
end
end //MAIN COUNTER END
这里我不知道如何合并这两个部分,我很想这样 如果开始 always@posedge时钟 /计数/ 别的 /* 几乎功能性地改变数字(当改变发生时立即)*/
将其添加到 if(start) else 中似乎可以完成工作,但仅在相当低频率时钟的上升沿上。据我所知,我不能在两个不同的 ALWAYS@ 中使用一个 reg。
/* // Clear previous number and store new number in shift register
shift[13:6] = 0;
shift[5:0] = number;
//BINARY TO BCD
for (i=0; i<6; i=i+1)
begin
if (shift[9:6] >= 5)
shift[9:6] = shift[9:6] + 3;
if (shift[13:10] >= 5)
shift[13:10] = shift[13:10] + 3;
shift = shift << 1;
end
units <= shift[9:6];
tens <= shift[13:10];
*/
dek7seg 是7段显示,100%正常(教授代码)。
dek7seg ss1(
.bits(units[3:0]),
.seg(DISP1[6:0])
);
dek7seg ss10(
.bits(tens[3:0]),
.seg(DISP2[6:0])
);
endmodule
您正在使用衍生时钟来控制您的主计数器。而是使用主时钟 MCLK
并使用 delay
的逻辑作为条件语句。
由于您希望在 number
发生变化时存储新值,因此您需要存储之前的 number
值并进行比较。
根据您的描述,您的代码应如下所示:
//MAIN COUNTER
always@ (posedge MCLK)
begin
if (start && &delay)
begin
/* your up/down logic here */
end
else if (number != prev_number)
begin // Clear previous number and store new number
prev_number <= number;
units <= new_units;
tens <= new_tens;
end
end
// Calculate new units and tens from number
always @* begin
shift[13:6] = 0;
shift[5:0] = number;
//BINARY TO BCD
for (i=0; i<6; i=i+1) begin
if (shift[9:6] >= 5)
shift[9:6] = shift[9:6] + 3;
if (shift[13:10] >= 5)
shift[13:10] = shift[13:10] + 3;
shift = shift << 1;
end
new_units = shift[9:6];
new_tens = shift[13:10];
end