VHDL 通用延迟 - 测试平台和配置

Question

我一直在为一些简单的 VHDL 门建模，但我似乎无法获得正确的时间延迟我有以下代码：

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY AND_4 IS
GENERIC (delay : delay_length := 0 ns);
PORT (a, b, c, d    :   IN      std_logic;
        x               :   OUT STD_logic);
END ENTITY AND_4;

 ARCHITECTURE dflow OF AND_4 IS
BEGIN
x <= ( a and b and c and d) AFTER delay;
END ARCHITECTURE dflow;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY TEST_AND_4   IS
END ENTITY TEST_AND_4;

ARCHITECTURE IO OF TEST_AND_4 IS
COMPONENT AND_4 IS
GENERIC (delay : delay_length := 0 ns);
PORT (a, b, c, d    :   IN      std_logic;
        x               :   OUT STD_logic);
END COMPONENT AND_4;
SIGNAL a,b,c,d,x    :   std_logic := '0';
BEGIN
G1 : AND_4 GENERIC MAP (delay => 5ns) PORT MAP (a,b,c,d,x);
PROCESS
VARIABLE error_count    :   integer:= 0;
BEGIN
WAIT FOR 1 NS;
a <= '1';
b <= '0';
c <= '0';
d <= '0';
ASSERT (x = '1') REPORT "output error" SEVERITY error;
    IF (x /= '1') THEN
        error_count := error_count + 1;
    END IF;
--Repeated test vector -- omitted
END PROCESS;
END ARCHITECTURE IO;

CONFIGURATION TESTER1 OF TEST_AND_4 IS
FOR IO
    FOR G1 : AND_4
        USE ENTITY work.AND_4(dflow)
        GENERIC MAP (delay);
    END FOR;
END FOR;
END CONFIGURATION TESTER1;

当我模拟模型时，我只得到了我添加到每个测试向量的 1 ns 延迟。我猜问题是我如何将延迟传递给测试台中的组件声明。我已经尝试了一些东西并重新阅读了我所拥有的书中的主题，但仍然没有快乐。有什么帮助吗？非常感谢 D

Answer 1

修改测试台中未标记的刺激过程：

    process
        variable error_count    :   integer:= 0;
    begin
        wait for 1 ns;
        a <= '1';
        -- b <= '0';
        -- c <= '0';
        -- d <= '0';
        -- assert (x = '1') report "output error" severity error;
        -- if (x /= '1') then
        --     error_count := error_count + 1;
        -- end if;
--repeated test vector -- omitted
        b <= '1';
        c <= '1';
        d <= '1';
        wait for 5 ns;
        wait for 5 ns;
        wait;
    end process;

简单地演示延迟表明通用延迟正在传递给实例化组件：

如果您得到不同的结果，也许您可以将您的问题转换为 Minimal, Complete, and Verifiable example，方法是确保该示例实际重现问题并且我们知道您的结果：

描述问题。 "It doesn't work" 不是问题陈述。告诉我们预期的行为应该是什么。告诉我们错误消息的确切措辞是什么，以及是哪一行代码产生的。在你的问题标题中写下问题的简要总结。

您留在测试台中的一点点刺激没有正确显示测试 and_4。

如果有更多的刺激，而您没有等待信号分配延迟机制隐含的脉冲抑制限制，除了那些烦人的断言之外，您什么也得不到。

参见 IEEE 标准 1076-2008 10.5。简单信号分配语句，5.2.1 概述，第 5 和 6 段：

The right-hand side of a simple waveform assignment may optionally specify a delay mechanism. A delay mechanism consisting of the reserved word transport specifies that the delay associated with the first waveform element is to be construed as transport delay. Transport delay is characteristic of hardware devices (such as transmission lines) that exhibit nearly infinite frequency response: any pulse is transmitted, no matter how short its duration. If no delay mechanism is present, or if a delay mechanism including the reserved word inertial is present, the delay is construed to be inertial delay. Inertial delay is characteristic of switching circuits: a pulse whose duration is shorter than the switching time of the circuit will not be transmitted, or in the case that a pulse rejection limit is specified, a pulse whose duration is shorter than that limit will not be transmitted.

Every inertially delayed signal assignment has a pulse rejection limit. If the delay mechanism specifies inertial delay, and if the reserved word reject followed by a time expression is present, then the time expression specifies the pulse rejection limit. In all other cases, the pulse rejection limit is specified by the time expression associated with the first waveform element.

(注意你可以去 10.5.2.2 Executing a simple assignment statement 看到 after time_expression is part of the waveform_element 而不是延迟机制）。

Answer 2

感谢您的帮助，但我今天早上在阅读 USER115520 的 post 后发现了问题。我设置的延迟是 'inertial'，一般设置为 5 ns。在我的测试台过程中，我只在输入信号变化之间设置了 1 ns 等待语句。因此，当正确的刺激和引入时，门不会执行转换。

我在 a=1 b=1 c=1 d=1 之后插入了 6 ns 的延迟，并从门得到了正确的响应

Answer 3

当然

ENTITY TEST_AND_4   IS
END ENTITY TEST_AND_4;

ARCHITECTURE IO OF TEST_AND_4 IS
COMPONENT AND_4 IS
  GENERIC (delay : delay_length := 0 ns);
  PORT (a, b, c, d  :   IN      std_logic;
        x               :   OUT STD_logic);
END COMPONENT AND_4;
  SIGNAL a,b,c,d,x  :   std_logic := '0';
BEGIN
  G1 : AND_4 GENERIC MAP (delay => 5 NS) PORT MAP (a,b,c,d,x);
PROCESS
VARIABLE error_count    :   integer:= 0;
BEGIN
  WAIT FOR 1 NS; -- Changed to 6 ns so that the wait is longer then the   
                 -- generic gate propagation delay
  a <= '1';
  b <= '1';
  c <= '1';
  d <= '1';
ASSERT (x = '1') REPORT "output error" SEVERITY error;
    IF (x /= '1') THEN
        error_count := error_count + 1;
    END IF;

我已经注意到我对上面的测试台模型所做的更改，现在看起来有点明显，但昨天它让我抓狂。干杯 D

'fix' 是将顺序测试平台模型中的 WAIT 值从 1 ns 更改为 6 ns。这给了门改变状态的时间，因为它有 5 ns 的惯性延迟。

  WAIT FOR 6 NS; -- Changed to 6 ns so that the wait is longer then the   
                 -- generic gate propagation delay

VHDL 通用延迟 - 测试平台和配置

VHDL Generic delay - test bench and config

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