两种 ARRAYS 类型的 VHDL 串联 std_logic

Question

您好，我正在尝试使用 ARRAYS 作为内存。我想将 4 个较小的 ARRAYS 连接成一个较大的 ARRAY。我试过使用符号来做到这一点：

MEM_STRING(1) <= MEM_CHAR(3) & MEM_CHAR(3) & MEM_CHAR(0) & MEM_CHAR(1);

但是编译器说它没有找到 & 字符的定义。 MEM_STRING(1) 是 28 位，每个 MEM_CHAR 是 7 位。我可以将每个 MEM_CHAR 转换为 std_logic_vector，分配给一个信号然后连接，但这似乎是一个很长的路要走。还有其他方法吗？

TYPE SEG7 IS ARRAY (6 DOWNTO 0) OF std_logic; 
TYPE REG_CHAR IS ARRAY (3 DOWNTO 0) OF SEG7; --Array block for characters
TYPE STRINGS IS ARRAY (27 DOWNTO 0) OF std_logic;
TYPE REG_STRINGS IS ARRAY (6 DOWNTO 0) OF STRINGS; --Array block for strings
SIGNAL MEM_CHAR          : REG_CHAR; --Assign character
SIGNAL MEM_STRING        : REG_STRINGS; --Assign String

这些是使用的 ARRAY 减速。最良好的问候 D

Answer 1

I could convert each MEM_CHAR to std_logic_vector, assign to a signal and then concatenate, but it seems like a very long way to go about things. Is there any other way to do this?

MEM_CHAR 和 std_logic_vector 没有密切关系。 MEM_CHAR的元素类型是SEG7，std_logic_vector的元素类型是std_ulogic.

您应该创建 REG_CHAR 类型的聚合并将其转换为字符串类型：

library ieee;
use ieee.std_logic_1164.all;

entity memchar is 
end entity;

architecture foo of memchar is

    TYPE SEG7 IS ARRAY (6 DOWNTO 0) OF std_logic; 
    TYPE REG_CHAR IS ARRAY (3 DOWNTO 0) OF SEG7; --Array block for characters
    TYPE STRINGS IS ARRAY (27 DOWNTO 0) OF std_logic;
    TYPE REG_STRINGS IS ARRAY (6 DOWNTO 0) OF STRINGS; --Array block for strings
    SIGNAL MEM_CHAR:           REG_CHAR; --Assign character
    SIGNAL MEM_STRING:         REG_STRINGS; --Assign String

    function to_strings (REGC: REG_CHAR) return STRINGS is
        variable retstr: STRINGS;
        subtype strings_range is natural range STRINGS'RANGE;
        variable retptr: strings_range;  -- default value is STRINGS'LEFT
    begin
        for i in REG_CHAR'RANGE loop   -- 3 downto 0
            for k in SEG7'RANGE loop   -- 6 downto 0
                retstr(retptr) := REGC(i)(k);
                if retptr /= 0 then      -- quit decrementing at 0
                    retptr := retptr - 1;
                end if;
            end loop;
        end loop;
        return retstr;
    end function;

begin
    -- MEM_STRING(1) <= MEM_CHAR(3) & MEM_CHAR(3) & MEM_CHAR(0) & MEM_CHAR(1);
    MEM_STRING(1) <=  to_strings(REG_CHAR'(MEM_CHAR(3),
                                           MEM_CHAR(3),
                                           MEM_CHAR(0),
                                           MEM_CHAR(1)
                                           )
                                 );

end architecture;

这个例子分析、阐述和模拟，告诉我们聚合的元素长度总和匹配STRINGS长度。

注意函数 to_strings.

中保留了从左到右的顺序

为了值得，仔细阅读所有这些迂回的定义是很痛苦的，更不用说提供 Minimal, Complete, and Verifiable example.

的问题了。

Answer 2

如果不是：

TYPE SEG7 IS ARRAY (6 DOWNTO 0) OF std_logic; 
TYPE STRINGS IS ARRAY (27 DOWNTO 0) OF std_logic;

你做到了：

subtype SEG7 IS std_logic_vector(6 DOWNTO 0) ; 
subtype STRINGS IS std_logic_vector(27 DOWNTO 0) ;

那么你可以这样做：

MEM_STRING(1) <= MEM_CHAR(3) & MEM_CHAR(3) & MEM_CHAR(0) & MEM_CHAR(1);

或：

MEM_STRING(1) <= MEM_CHAR(3) & MEM_CHAR(2) & MEM_CHAR(1) & MEM_CHAR(0);

您也可以跳过创建子类型 SEG7 和 STRINGS 并完成：

--Array block for characters    
TYPE REG_CHAR IS ARRAY (3 DOWNTO 0) OF std_logic_vector(6 DOWNTO 0) ; 
--Array block for strings
TYPE REG_STRINGS IS ARRAY (6 DOWNTO 0) OF std_logic_vector(27 DOWNTO 0) ; 
SIGNAL MEM_CHAR          : REG_CHAR; --Assign character
SIGNAL MEM_STRING        : REG_STRINGS; --Assign String

两种 ARRAYS 类型的 VHDL 串联 std_logic

VHDL concatenation of two ARRAYS types std_logic

vhdl