for 循环生成在 always 块中

Question

我正在尝试通过 VGA 创建 32 色条纹。

     generate
     genvar i;

     always @(posedge vga_clk) begin
         if (x_num == 10'h3FF) 
             RGB = 16'b00000_000011_00011;
     for (i = 1; i < 32; i = i + 1) begin: rgb_gen
40:      else if ((i * 20 < x_num) && (x_num < (i + 1) * 20)) begin
             RGB = RGB << i;
         end
     end

     end
     endgenerate

但是出现错误：

Error (10170): Verilog HDL syntax error at top.v(40) near text "else"; expecting "end"

在我看来，结果必须如下：

always @(posedge vga_clk) begin
    if (x_num == 10'h3FF) 
        RGB = 16'b00000_000011_00011;
    else if ((0 < x_num) && (x_num < 20))
        RGB = RGB << 0;
    else if ((20 < x_num) && (x_num < 40))
        RGB = RGB << 1;
    ..................
end

我做错了什么？

Answer 1

您不能在程序代码块中间嵌入 generate 块。我想你想要的是

integer i;

    always @(posedge vga_clk) begin
       RGB = 0;  
       if (x_num == 10'h3FF) 
             RGB = 16'b00000_000011_00011;
         else 
         for (i = 1; i < 32; i = i + 1)
            if ((i * 20 < x_num) && (x_num < (i + 1) * 20))
             RGB = RGB << i;
       end

for 循环生成在 always 块中

For loop generation in always block

verilog

fpga