case/always 语句的 Verilog 问题

Question

我已经使用给定的示例代码为 class 编写了此模块，但在尝试编译时出现错误 - 我认为这可能是由于我使用输入的方式 (或者只是一个语法错误），所以我试图用数组来做 - 我评论的方法是否正确？我应该使用串联吗？

module ledSwitch(LEDR, SW);
    input [9:0] SW; //switches and led
    output [0] LEDR;
 
    mux7to1 u0(
        .s0(SW[0]),//input switches to mux
        .s1(SW[1]),
        .s2(SW[2]),
        .s3(SW[3]),
        .s4(SW[4]),
        .s5(SW[5]),
        .s6(SW[6]),
        .s7(SW[7]),
        .s8(SW[8]),
        .s9(SW[9]),
        //.inputs([SW[0], [SW[1], [SW[2], [SW[3], [SW[4], [SW[5], [SW[6]])
        //.muxSelect([SW[7], [SW[8], [SW[9])
        .l(LEDR[0]) //input led output to mux
        );
endmodule

module mux7to1(s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, l);
    input s0;
    input s1;
    input s2;
    input s3;
    input s4;
    input s5;
    input s6;
    input s7;
    input s8;
    input s9;
    //input inputs[6:0]
    //input muxSelect[2:0]

    output l;

    reg Out; //declare the output signal for the always block

    always@(*) //declare always block
    begin
        case ([s9, s8, s7])//muxSelect[2:0] //start case statement
            3'b000: Out = s0; //case 0, A
            3'b001: Out = s3; //case 1, D
            3'b010: Out = s1; //case 2, B
            3'b011: Out = s5 //case 3, F
            3'b100: Out = s0; //case 4, A
            3'b101: Out = s4; //case 5, E
            3'b110: Out = s2; //case 6, C
            3'b111: Out = s6; //case 7, G
            default: Out = 0; //Default        
        endcase
    end
    assign l = Out;
endmodule

错误信息如下：

Info: *******************************************************************

Info: Running Quartus II 64-Bit Analysis & Synthesis

Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition

Info: Processing started: Tue Feb 2 14:53:06 2016

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab2_1 -c Lab2_1

Warning (20028): Parallel compilation is not licensed and has been disabled

Error (10170): Verilog HDL syntax error at Lab2_1.v(43) near text "["; expecting an operand

Error (10170): Verilog HDL syntax error at Lab2_1.v(45) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(46) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(47) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(48) near text "3"; expecting ";"

Error (10170): Verilog HDL syntax error at Lab2_1.v(49) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(50) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(51) near text "3"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(52) near text "default"; expecting "end"

Error (10170): Verilog HDL syntax error at Lab2_1.v(53) near text "endcase"; expecting "end"

Error (10112): Ignored design unit "mux7to1" at Lab2_1.v(24) due to previous errors

Info (12021): Found 0 design units, including 0 entities, in source file Lab2_1.v

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 11 errors, 1 warning

Error: Peak virtual memory: 959 megabytes

Error: Processing ended: Tue Feb 2 14:53:23 2016

Error: Elapsed time: 00:00:17

Error: Total CPU time (on all processors): 00:00:51

Error (293001): Quartus II Full Compilation was unsuccessful. 13 errors, 1 warning

Answer 1

您需要使用连接运算符：case ({s9, s8, s7})

您还有一些语法错误，例如缺少分号，需要更正。

最后，您需要在 ledSwitch 模块中正确定义输出。

case/always 语句的 Verilog 问题

Verilog issue with case/always statement

verilog

case-statement

quartus