这个代码结构是否朝着正确的方向发展？

Question

我正在尝试使用 7 段显示器。我写了一个模块，我想接受 4 个输入并更改十六进制输出。 unpacked/packed 数组似乎有问题，我真的不知道我到底在做什么。非常感谢任何帮助。

module hexDisplay(hex, c0, c1, c2, c3);
    input c0;
    input c1;
    input c2;
    input c3;      
    output hex[6:0];       
    reg out[6:0];

    always@(*)
    begin
        case({c3, c2, c1, c0})
            4'b0000:out [5:0] = 1;
            // 0001-1111 go here
            //...
            default:out [6:0] = 0;
         endcase
      assign hex = out;
     end

endmodule

错误：

Error (10773): Verilog HDL error at lab2pre.v(55): declaring module ports or function arguments with unpacked array types requires SystemVerilog extensions Error (10133): Verilog HDL Expression error at lab2pre.v(61): illegal part select of unpacked array "out"

Error (10133): Verilog HDL Expression error at lab2pre.v(62): illegal part select of unpacked array "out"

Error (10048): Verilog HDL error at lab2pre.v(64): values cannot be assigned directly to all or part of array "hex" - assignments must be made to individual elements only

Error (10137): Verilog HDL Procedural Assignment error at lab2pre.v(64): object "hex" on left-hand side of assignment must have a variable data type

Error (10044): Verilog HDL error at lab2pre.v(64): expression cannot reference entire array "out"

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 1 warning Error: Peak virtual memory: 959 megabytes Error: Processing ended: Tue Feb 2 17:33:35 2016 Error: Elapsed time: 00:00:15 Error: Total CPU time (on all processors): 00:00:46

Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 1 warning

Answer 1

尝试这样的事情。将范围说明符 ([6:0]) 移到信号名称的左侧，并将 assign 移到 always 块之外。

module hexDisplay(hex, c0, c1, c2, c3);
    input c0;
    input c1;
    input c2;
    input c3;      
    output [6:0] hex;
    reg [6:0] out;

    always@(*)
    begin
        case({c3, c2, c1, c0})
            4'b0000:out [5:0] = 1;
            // 0001-1111 go here
            //...
            default:out [6:0] = 0;
         endcase
     end
     assign hex = out;

endmodule

Answer 2

2 个错误：

您需要 "packed" 数组而不是 "unpacked" 数组 "out" & "hex" 网。

SystemVerilog supports both packed arrays and unpacked arrays of data. The term packed array is used to refer to the dimensions declared before the data identifier name. The term unpacked array is used to refer to the dimensions declared after the data identifier name.

位[7:0] c1； // 标量位类型的打包数组真实的你[7:0]； // 实际类型的解包数组

A packed array is a mechanism for subdividing a vector into subfields, which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits.

An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.

因此在代码中，您需要 out & hex 用作连续位向量，那么它应该是打包数组，而不是解包数组。

参考 Systemverilog LRM 的主题 7.4。
assign 语句为十六进制，不能在 always 块中使用。因为一个 assign 语句仅用于建模组合逻辑，它连续执行。所以assign语句被称为 'continuous assignment statement' 因为没有敏感列表。

所以不能在always块内，按照敏感度列表。

所以你最终的工作代码如下：

module hexDisplay(hex, c0, c1, c2, c3);
    input c0;
    input c1;
    input c2;
    input c3;      
    output [6:0] hex;       
    reg [6:0] out;

    always@(*)
    begin
        case({c3, c2, c1, c0})
            4'b0000:out [5:0] = 1;
            // 0001-1111 go here
            //...
            default:out [6:0] = 0;
         endcase
     end

    assign hex = out;
endmodule

Answer 3

always 块中的任何变量都必须是 reg ，这里你在 always 中分配十六进制，默认情况下是 wire 所以如果你在 always 之外分配十六进制，你将获得免费编译代码。

这个代码结构是否朝着正确的方向发展？

Is this code structure going in the right direction?

verilog

quartus