ModelSim 不编译重载函数和未定义范围类型

Question

我运行正在使用 ModelSim 10.3d，并且我的程序包中有以下代码：

package core_params_types is
    type array_1d_logic is array (natural range <>) of std_logic;
type array_1d_logic_vector is array (natural range <>) of std_logic_vector (natural range <>);
type array_2d_logic is array (natural range <>, natural range <>) of std_logic;
type array_2d_logic_vector is array (natural range <>, natural range <>) of std_logic_vector (natural range <>);

function or_reduce_2d_logic(a : array_2d_logic; i : integer) return std_logic;
function or_reduce_2d_logic_vector(a : array_2d_logic_vector; i : integer) return std_logic_vector;

function bitwise_cmp(a : std_logic_vector; b : std_logic_vector) return std_logic;
function bitwise_cmp(a : std_logic; b : std_logic) return std_logic;

function full_adder(a : std_logic_vector; b : std_logic_vector; ci : std_logic) return std_logic_vector;

function sign_extend(a : std_logic_vector; b : integer) return std_logic_vector;
function sign_extend(a : std_logic; b : integer) return std_logic_vector;
function logic_extend(a : std_logic_vector; b : integer) return std_logic_vector;
function logic_extend(a : std_logic; b : integer) return std_logic_vector;

ModelSim 出现以下错误：

-- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package ATTRIBUTES
# -- Loading package std_logic_misc
# -- Compiling package core_params_types
# ** Error: core_params_types.vhd(40): near "<>": syntax error
# ** Error: core_params_types.vhd(42): near "<>": syntax error
# ** Error: core_params_types.vhd(45): (vcom-1136) Unknown identifier "array_2d_logic_vector".
# ** Error: core_params_types.vhd(48): (vcom-1295) Function "bitwise_cmp" has already been defined in this region.
# ** =====> Prior declaration of "bitwise_cmp" is at core_params_types.vhd(47).
# ** Error: core_params_types.vhd(53): (vcom-1295) Function "sign_extend" has already been defined in this region.
# ** =====> Prior declaration of "sign_extend" is at core_params_types.vhd(52).
# ** Error: core_params_types.vhd(55): (vcom-1295) Function "logic_extend" has already been defined in this region.
# ** =====> Prior declaration of "logic_extend" is at core_params_types.vhd(54).
# ** Error: core_params_types.vhd(310): VHDL Compiler exiting

.do 文件包含以下命令：

transcript on
if {[file exists rtl_work]} {
    vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vcom -2008 -work work {core_params_types.vhd}
vcom -2008 -work work {alu.vhd}

vcom -2008 -work work {tb_alu.vhd}
vcom -2008 -work work {alu.vhd}

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L rtl_work -L work -voptargs="+acc"  tb_alu

add wave *
view structure
view signals
run -all

我运行 Quartus的ModelSim仿真，编译代码没有错误，生成电路。 ModelSim 表示函数已经定义。这是正确的，但它们有不同的类型，所以它们应该被重载。而且ModelSim不理解数组类型的声明。

Answer 1

类型声明

type array_1d_logic_vector is array (natural range <>) of std_logic_vector (natural range <>);

无效。您没有声明元素类型的索引类型。而是尝试：

type array_1d_logic_vector is array (natural range <>) of std_logic_vector;

您在对象声明中约束元素子类型，例如：

variable foo: array_1d_logic_vector(0 to 1)(7 downto 0);

其中元素子类型约束为7到0，数组约束为0到1。

参见 IEEE Std 1076-2008 5.3.2 数组类型，5.3.2.1 通用段落 6：

An unbounded array definition in which the element subtype indication denotes either an unconstrained composite subtype or a subtype that is not a composite subtype defines an array type and a name denoting that type. For each object that has the array type, the number of indices, the type and position of each index, and the subtype of the elements are as in the type definition. The index subtype for a given index position is, by definition, the subtype denoted by the type mark of the corresponding index subtype definition. The values of the left and right bounds of each index range are not defined, but shall belong to the corresponding index subtype; similarly, the direction of each index range is not defined. The symbol <> (called a box) in an index subtype definition stands for an undefined range (different objects of the type need not have the same bounds and direction).

在 5.3.2.1（接近尾声）中找到了一个代码示例。

如果第二种形式看起来很容易搞砸，那确实是。您可以使用具有不同子类型约束且在长度不同时不兼容的元素来声明相同类型的对象。

没有看到使用原始成功合成的任何合成操作的日志文件输出将不符合 VHDL 标准。

如果不仔细梳理所有内容，您的测试用例包声明与示例代码中给出的行号不匹配。看起来你在包体中重新声明函数（注意行号 310）。尝试删除重复的函数声明。

（您也可以提供一个实际的 Minimal, Complete, and Verifiable example，它会很好地告诉您到底发生了什么）。

ModelSim 不编译重载函数和未定义范围类型

ModelSim does not compile overloaded functions and undefined range types

overloading

vhdl

modelsim

intel-fpga

quartus