在结构化的VHDL中连接执行为adder/subtractor

Question

所以我有以下 VHDL 代码来实现 Nbit adder/subtractor，仅使用 2:1 多路复用器、反相器（翻转位）和全加器。我在将加法器的进位连接到下一个进位时遇到问题，而第一个加法器的进位为 i_Control。任何帮助将不胜感激:)。

    library IEEE;
use IEEE.std_logic_1164.all;
use work.all;

entity add_subtract is
  generic(N   : integer := 16);
  port(i_M    : in std_logic_vector(N-1 downto 0);
       i_N    : in std_logic_vector(N-1 downto 0);
       i_Control  : in std_logic_vector(N-1 downto 0);
       o_S    : out std_logic_vector(N-1 downto 0));

end add_subtract;

architecture structure of add_subtract is

component bit_adder
    port(i_X     : in std_logic;
             i_Y     : in std_logic;
             i_Cin   : in std_logic;
             o_Ss    : out std_logic;
         o_Couts : out std_logic);
end component;

component inverter
    port(i_A  : in std_logic;
         o_F  : out std_logic);
end component;

component bit_mux
    port(i_X  : in std_logic;
         i_Y  : in std_logic;
             i_S  : in std_logic;
             o_N  : out std_logic);
end component;

signal compvalue, muxvalue, addervalue : std_logic_vector(N-1 downto 0);
signal sel, carry : std_logic_vector(N-1 downto 0);
signal k : integer := 0;
begin

carry(0) <= i_Control(0);

G1: for i in 0 to N-1 generate
one_comp: inverter
    port map(i_A     => i_N(i),
         o_F     => compvalue(i));

mux: bit_mux
    port map(i_X     => i_N(i),
         i_Y     => compvalue(i),
         i_S     => i_Control(i),
         o_N     => muxvalue(i));

struct_adder: bit_adder
    port map(i_X     => i_M(i),
         i_Y     => muxvalue(i),
         i_Cin   => carry(i),
         o_Ss    => o_S(i),
         o_Couts => carry(i));

end generate;

end structure;

Answer 1

进位数组加长一个：

signal carry : std_logic_vector(N downto 0); -- was N-1

并更改此：

     o_Couts => carry(i));

对此：

     o_Couts => carry(i+1));

在您的生成语句中保留 i_Cin 进位输入关联。

如果最后一个进位不通过输出端口传送，网络将在合成过程中被吃掉。

在结构化的VHDL中连接执行为adder/subtractor

Connect carry out to carry in for adder/subtractor in structural VHDL

vhdl