在 vhdl 中创建线性搜索算法

Question

我正在尝试使用 vhdl 实现线性搜索算法我的代码是

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity q1 is port(
input : in integer;
output : out integer
);
end q1;
architecture beh of q1 is
type my_array is array (0 to 6) of integer;
constant sequence: my_array := (0,1,2,3,4,5,6,7);
begin
process(input) 

for i in sequence' range generate
    begin
        GenIf: if (input=my_array(i)) generate then
            output <=input;
        else
    output <=0; 
                end generate GenIf;
            end generate;
    end process;
    end beh;

我收到的错误消息是：

Error (10500): VHDL syntax error at Search.vhd(16) near text "for"; expecting "begin", or a declaration statement

Error (10500): VHDL syntax error at Search.vhd(18) near text "generate"; expecting "then"

Error (10500): VHDL syntax error at Search.vhd(20) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Search.vhd(22) near text "end generate GenIf;"; expecting "end", or "(", or an identifier, or a sequential statement

Error (10500): VHDL syntax error at Search.vhd(22) near text Info: Found 0 design units, including 0 entities, in source file search.vhd

Answer 1

纠正第一个错误或第一对错误总是值得的。在那之后，它变得毫无意义，因为后续的错误取决于第一个或两个。所以，我看了前两个：

Error (10500): VHDL syntax error at Search.vhd(16) near text "for"; expecting "begin", or a declaration statement

您的进程需要 begin 语句。所有进程都需要一个begin语句：

process(input)
begin

Error (10500): VHDL syntax error at Search.vhd(18) near text "generate"; expecting "then"

Generate 语句不属于进程内部。（实际上，您可以将进程放在 generate 语句中）。我认为您需要修改生成语句。您只需要一个普通的 for loop 和 if 语句：

process(input) 
begin
for i in sequence'range loop
        GenIf: if input=sequence(i)  then

（你的意思是 sequence 而不是 my_array。）

更正这些之后，您会发现还有更多不同的错误需要更正，由于之前的错误而没有报告。

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