计数器溢出或条件不是肉

Question

我正在 CoolRunner 2 上做一个 60 分钟计时器的小项目。我想驱动四个 7 段显示器来发展我在 VHDL 方面的新技能，我主要是一名模拟工程师，所以如果你有任何提示我在 VHDL 中，我会向他们开放。但我的问题是：我有四个计数器，它们一起计数到 59 分钟和 59 秒，然后重置，但我的第三个计数器没有递增 (counter3)。当我运行测试台时，它只进行了 59 秒然后重置。

下面我附上了柜台 1、2、3、4 的柜台代码。有人能看出任何拼写错误或明显错误吗？

--counter1-------------------------------------------------------------     
Process ( CLK1Hz,RST,SW1,overflow4 )
begin
    if (RST = '0') or (overflow4 = '1')  then
        Counter1 <=0;
    elsif Rising_edge (CLK1Hz)then
        if (SW1 = '1' )  then
            counter1 <= counter1 + 1;
                if Counter1 = 8 then
                    overflow1 <= '1';
                elsif counter1 = 9 then
                    Counter1 <= 0;
                    overflow1 <= '0';
                end if;
        end if;
end if;
end process;

--counter2---------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow1,overflow4,counter1 )
begin
    if (RST = '0') or (overflow4 = '1') then
        Counter2 <=0;
    elsif Rising_edge (CLK1Hz) then
        if (SW1 = '1' ) and (overflow1 = '1') then
            counter2 <= counter2 + 1;
                if counter2 = 5 and counter1 = 8 then
                    overflow2 <= '1';
                elsif counter2 = 5 and counter1 = 9 then
                    counter2 <= 0;
                    overflow2 <= '0';
                end if;
        end if;     
end if;
end process;

--counter3----------------------------------------------------------------   
Process ( CLK1Hz,RST,SW1,overflow2,overflow4,counter1,counter2 )
begin
   if (RST = '0') or (overflow4 = '1') then
    Counter3 <=0;
   elsif Rising_edge (CLK1Hz) then
        if (SW1 = '1' ) and (overflow2 = '1') then
            counter3 <= counter3 + 1;
                if counter3 = 9 and counter2 = 5 and counter1 = 8 then
                    overflow3 <= '1';
                elsif counter3 = 9 and counter2 = 5 and counter1 = 9 then
                    counter3 <= 0;
                    overflow3 <= '0';
                end if;
        end if;
end if;
end process;    

--counter4----------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow3,overflow4,counter1,counter2,counter3 )
begin
    if (RST = '0') or (overflow4 = '1') then
        Counter4 <=0;
    elsif Rising_edge (CLK1Hz) then
        if(SW1 = '1' ) and (overflow3 = '1') then
            counter4 <= counter4 + 1;
                if counter4 = 6 then
                    counter4 <= 0;
                    overflow4 <= '1';
                else overflow4 <= '0';
                end if;
        end if;
end if;
end process;

更新 1：问题似乎是 Integer 不接受和起作用，所以我尝试将它转换为无符号，但这不会出问题。

Answer 1

计数器 3 没有递增，因为 overflow2 从未设置为“1”。让我们看一下 counter2:

过程的时钟同步部分

    if (SW1 = '1' ) and (overflow1 = '1') then
        counter2 <= counter2 + 1;
            if counter2 = 5 and counter1 = 8 then
                overflow2 <= '1';
            elsif counter2 = 5 and counter1 = 9 then
                counter2 <= 0;
                overflow2 <= '0';
            end if;
    end if;

寄存器overflow2仅在SW = '1'、overflow1 = '1'、counter2 = 5和counter1 = '8'时设置。但是，overflow1 = '1' 和 counter1 = 8 永远不会同时为真。当counter1的旧值为8时设置寄存器overflow1，但是overflow1将是'1' 只有和counter1 = 9.

你必须在这个过程中修复if语句的嵌套，这样，只有counter2的增量取决于overflow1。设置 overflow2 必须仅取决于计数器状态（和 SW1）。所以，上面的要改成：

  if (SW1 = '1' ) then
    if (overflow1 = '1') then
      counter2 <= counter2 + 1;
    end if;

    if counter2 = 5 and counter1 = 8 then
      overflow2 <= '1';
    elsif counter2 = 5 and counter1 = 9 then
      counter2 <= 0;
      overflow2 <= '0';
    end if;
  end if;

同样适用于 counter3 和 counter4 的流程。

在最后一个过程中，只能设置信号overflow4，因为一旦设置，异步复位就会一直执行。正如您已经描述的那样，只需使用 counter4 的同步重置。 overflow4 还应同步重置其他计数器，但我将把它留作练习。

将所有这些放在一起，您将获得以下代码，并将其嵌入到具有时钟生成功能的测试平台中：

library ieee;
use ieee.std_logic_1164.all;

entity counter2 is
end entity counter2;

architecture counter2 of counter2 is
  signal counter1, counter2, counter3, counter4 : integer := 0;
  signal overflow1, overflow2, overflow3, overflow4 : std_logic := '0';
  signal RST : std_logic := '1';
  signal SW1 : std_logic := '1';
  signal CLK1Hz : std_logic := '1';

begin  -- architecture counter2

  -- clock generation
  CLK1Hz <= not CLK1Hz after 500 ms;

--counter1-------------------------------------------------------------     
  Process ( CLK1Hz,RST,SW1,overflow4 )
  begin
    if (RST = '0') or (overflow4 = '1')  then
      Counter1 <=0;
    elsif Rising_edge (CLK1Hz)then
      if (SW1 = '1' )  then
        counter1 <= counter1 + 1;
        if Counter1 = 8 then
          overflow1 <= '1';
        elsif counter1 = 9 then
          Counter1 <= 0;
          overflow1 <= '0';
        end if;
      end if;
    end if;
  end process;

--counter2---------------------------------------------------------------
  Process ( CLK1Hz,RST,SW1,overflow1,overflow4,counter1 )
  begin
    if (RST = '0') or (overflow4 = '1') then
      Counter2 <=0;
    elsif Rising_edge (CLK1Hz) then
      if (SW1 = '1' ) then
        if (overflow1 = '1') then
          counter2 <= counter2 + 1;
        end if;
        if counter2 = 5 and counter1 = 8 then
          overflow2 <= '1';
        elsif counter2 = 5 and counter1 = 9 then
          counter2 <= 0;
          overflow2 <= '0';
        end if;
      end if;     
    end if;
  end process;

--counter3----------------------------------------------------------------   
  Process ( CLK1Hz,RST,SW1,overflow2,overflow4,counter1,counter2 )
  begin
    if (RST = '0') or (overflow4 = '1') then
      Counter3 <=0;
    elsif Rising_edge (CLK1Hz) then
      if (SW1 = '1' ) then
        if (overflow2 = '1') then
          counter3 <= counter3 + 1;
        end if;

        if counter3 = 9 and counter2 = 5 and counter1 = 8 then
          overflow3 <= '1';
        elsif counter3 = 9 and counter2 = 5 and counter1 = 9 then
          counter3 <= 0;
          overflow3 <= '0';
        end if;
      end if;
    end if;
  end process;    

--counter4----------------------------------------------------------------
  Process ( CLK1Hz,RST,SW1,overflow3,overflow4,counter1,counter2,counter3 )
  begin
    if (RST = '0') then-- or (overflow4 = '1') then
      Counter4 <=0;
    elsif Rising_edge (CLK1Hz) then
      if(SW1 = '1' ) then
        if (overflow3 = '1') then
          counter4 <= counter4 + 1;
        end if;

        if counter4 = 6 then
          counter4 <= 0;
          overflow4 <= '1';
        else overflow4 <= '0';
        end if;
      end if;
    end if;
  end process;

end architecture counter2;

以下是模拟前100秒的截图：

计数器溢出或条件不是肉

Counter overflow or condition not meat

variables

case

vhdl