wait 必须包含带 until 关键字的条件子句

Question

以下 VHDL 将用于测试 booth multiplier。在分析和阐述过程中，我在第一个等待语句中不断收到错误："wait statement must contain condition clause with until keyword" 我有几个这样写的工作测试台（即信号分配，等待 x ns，其他分配，等待 x ns ...）。我似乎找不到可能是什么错误。

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY BoothMultiplier_32_test IS
END BoothMultiplier_32_test;

ARCHITECTURE test_arch OF BoothMultiplier_32 IS

SIGNAL A_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL B_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL result_test  :   STD_LOGIC_VECTOR (63 downto 0);

COMPONENT BoothMultiplier_32
    PORT (
        dataA, dataB    :   IN STD_LOGIC_VECTOR (31 downto 0);
        result          :   OUT STD_LOGIC_VECTOR (63 downto 0)
    );
END COMPONENT;

BEGIN
    DUT1: BoothMultiplier_32 
    PORT MAP(
        dataA=>A_test,
        dataB=>B_test,
        result=>result_test
    );

    testing : PROCESS
    BEGIN
        wait for 10 ns;
        A_test<=x"0000000A";
        B_test<=x"0000000A";
        --wait for 10 ns;
        --A_test<=x"10000000";
        --B_test<=x"00000010";
        --wait for 10 ns;
        --A_test<=x"FFFFFFFF";
        --B_test<=x"FFFFFFFF";
        wait;
    END PROCESS testing;

END ARCHITECTURE test_arch;

Answer 1

您的代码中唯一可观察到的错误是：

ARCHITECTURE test_arch OF BoothMultiplier_32 IS

应该是：

ARCHITECTURE test_arch OF BoothMultiplier_32_test IS

在您的实体和架构对之前添加一个虚拟 BoothMultiplier_32 并使用上述更正：

library ieee;
use ieee.std_logic_1164.all;

entity boothmultiplier_32 is
    port (
        dataa, datab    :   in std_logic_vector (31 downto 0);
        result          :   out std_logic_vector (63 downto 0)
    );
end entity;

architecture foo of boothmultiplier_32 is
begin
end architecture;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY BoothMultiplier_32_test IS
END BoothMultiplier_32_test;

ARCHITECTURE test_arch OF BoothMultiplier_32_test IS

SIGNAL A_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL B_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL result_test  :   STD_LOGIC_VECTOR (63 downto 0);

COMPONENT BoothMultiplier_32
    PORT (
        dataA, dataB    :   IN STD_LOGIC_VECTOR (31 downto 0);
        result          :   OUT STD_LOGIC_VECTOR (63 downto 0)
    );
END COMPONENT;

BEGIN
    DUT1: BoothMultiplier_32 
    PORT MAP(
        dataA=>A_test,
        dataB=>B_test,
        result=>result_test
    );

    testing : PROCESS
    BEGIN
        wait for 10 ns;
        A_test<=x"0000000A";
        B_test<=x"0000000A";
        --wait for 10 ns;
        --A_test<=x"10000000";
        --B_test<=x"00000010";
        --wait for 10 ns;
        --A_test<=x"FFFFFFFF";
        --B_test<=x"FFFFFFFF";
        wait;
    END PROCESS testing;

END ARCHITECTURE test_arch;

然后代码使用详细说明和运行目标 boothMultiplier_32_test 进行分析、详细说明和运行（虽然没有做任何有趣的事情，但 none 显示正确连接的情况较少).

或许您可以告诉我们您在使用什么工具时遇到了问题？

wait 必须包含带 until 关键字的条件子句

wait must contain condition clause with until keyword

vhdl