无法让 VHDL 顺序乘法器正确乘法

Question

我有一个学校实验室，我必须做关于在 VHDL 中创建顺序乘法器。我的问题发生在为顺序乘法器制作有限状态机之前。我无法让基本模型正确相乘，我想我的测试台有问题但我不能 100% 确定这一点。我仍然怀疑问题出在我的代码中。

顶层设计（基本上就是调用D-Flip-Flops、MUX和Adder）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity toplvds is

    port( A,B: in std_logic_vector(3 downto 0);
            Zero: in std_logic_vector(3 downto 0);
            clk, clr, load, loadP, sb: in std_logic;
            Po: out std_logic_vector(7 downto 0));

end toplvds;

architecture Behavioral of toplvds is

component dffa
    port( dina: in std_logic_vector(3 downto 0);
            clr, clk, load: in std_logic;
            q: out std_logic_vector(3 downto 0));
end component;

component dffb
    port( dinb: in std_logic_vector(3 downto 0);
            clr, clk, load, sb: in std_logic;
            qb0: out std_logic);
end component;

component mux
    port( d0,d1: in std_logic_vector(3 downto 0);
            s: in std_logic;
            y: out std_logic_vector(3 downto 0));
end component;

component adder
    port( a,b: in std_logic_vector(3 downto 0);
            cry: out std_logic;
            r: out std_logic_vector(3 downto 0));
end component;

component dffP
    port( dinp: in std_logic_vector(3 downto 0);
            carry: in std_logic;
            clr, clk, loadP, sb: in std_logic;
            PHout: out std_logic_vector (3 downto 0);
            P: out std_logic_vector(7 downto 0));
end component;

signal Wire1: std_logic_vector(3 downto 0);
signal Wire2: std_logic_vector(3 downto 0);
signal Wire3: std_logic;
signal Wire4: std_logic_vector(3 downto 0);
signal Wire5: std_logic_vector(3 downto 0);
signal Wire6: std_logic_vector(3 downto 0);
signal Wire7: std_logic;

begin

    Wire1 <= Zero;

    u1: dffa port map (dina=>A,clr=>clr,clk=>clk,load=>load,q=>Wire2);
    u2: dffb port map (dinb=>B,clr=>clr,clk=>clk,load=>load,sb=>sb,qb0=>Wire3);
    u3: mux port map (d0=>Wire2,d1=>Wire1,s=>Wire3,y=>Wire4);
    u4: adder port map (a=>Wire6,b=>Wire4,cry=>Wire7,r=>Wire5);
    u5: dffp port map (dinp=>Wire5,carry=>Wire7,clr=>clr,clk=>clk,loadP=>loadP,sb=>sb,PHout=>Wire6,P=>Po);

end Behavioral;

被乘数的 D 触发器

library ieee;
use ieee.std_logic_1164.all;
entity dffa is 
    port( dina: in std_logic_vector(3 downto 0);
            clr, clk, load: in std_logic;
            q: out std_logic_vector(3 downto 0));
end dffa;

architecture beh of dffa is
begin
    process(clk,clr)
    begin 
        if(clr = '1') then
            q <= ( others => '0');
        elsif (rising_edge(clk)) then
            if(load = '1') then
                q <= dina;
            end if;
        end if;
    end process;
end beh;

用于乘法器的 D 触发器

library ieee;
use ieee.std_logic_1164.all;
entity dffb is 
    port( dinb: in std_logic_vector(3 downto 0);
            clr, clk, load, sb: in std_logic;
            qb0: out std_logic);
end dffb;
architecture beh of dffb is
signal q: std_logic_vector(3 downto 0);
begin
    qb0 <= q(0);
    process(clk,clr, load, sb)
    begin 
        if(clr = '1') then
            q <= ( others => '0');
        elsif (rising_edge(clk)) then
            if(load = '1') then
                q <= dinb;
            elsif (sb = '1') then
                q <= '0' & q ( 3 downto 1); 
            end if;
        end if;
    end process;        
end beh;

MUX

library ieee;
use ieee.std_logic_1164.all;
entity mux is 
    port( d0,d1: in std_logic_vector(3 downto 0);
            s: in std_logic;
            y: out std_logic_vector(3 downto 0));

end mux;

architecture beh of mux is  

begin

    y <= d0 when s = '1' else d1;

end beh;

加法器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity adder is 
    port( a,b: in std_logic_vector(3 downto 0);
            cry: out std_logic;
            r: out std_logic_vector(3 downto 0));
end adder;

architecture beh of adder is
    signal temp : std_logic_vector(4 downto 0); 
begin
    temp <= ('0' & a) + ('0' & b);

   r <= temp(3 downto 0); 
   cry <= temp(4);
end beh;

产品的 D 触发器

library ieee;
use ieee.std_logic_1164.all;

entity dffp is 
    port( dinp: in std_logic_vector(3 downto 0);
            carry: in std_logic;
            clr, clk, loadP, sb: in std_logic;
            PHout: out std_logic_vector (3 downto 0);
            P: out std_logic_vector(7 downto 0));
end dffp;

architecture beh of dffp is
signal q: std_logic_vector(7 downto 0);
begin
    --qp0 <= q(0);
    process(clk,clr, loadP, sb)
    begin 
        if(clr = '1') then
            q <= ( others => '0');
        elsif (rising_edge(clk)) then
            if(loadP = '1') then
                --q <= "00000000";
                q(7 downto 4) <= dinp;
            elsif (sb = '1') then
                q <= carry & q ( 7 downto 1);   
            --else 
                --q(7 downto 4) <= dinp;
            end if;
        end if;
    end process;

    PHout <= q(7 downto 4); 
    P <= q;

end beh;

测试台代码

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY toplvds_tb IS
END toplvds_tb;

ARCHITECTURE behavior OF toplvds_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT toplvds
    PORT(
         A : IN  std_logic_vector(3 downto 0);
         B : IN  std_logic_vector(3 downto 0);
         Zero : IN  std_logic_vector(3 downto 0);
         clk : IN  std_logic;
         clr : IN  std_logic;
         load : IN  std_logic;
         loadP : IN  std_logic;
         sb : IN  std_logic;
         Po : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal A : std_logic_vector(3 downto 0) := (others => '0');
   signal B : std_logic_vector(3 downto 0) := (others => '0');
   signal Zero : std_logic_vector(3 downto 0) := (others => '0');
   signal clk : std_logic := '0';
   signal clr : std_logic := '0';
   signal load : std_logic := '0';
   signal loadP : std_logic := '0';
   signal sb : std_logic := '0';

    --Outputs
   signal Po : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: toplvds PORT MAP (
          A => A,
          B => B,
          Zero => Zero,
          clk => clk,
          clr => clr,
          load => load,
          loadP => loadP,
          sb => sb,
          Po => Po
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin

        A <= "1011";
        B <= "1101";
        Zero <="0000";

        load <= '0';
        sb <= '0';
        clr <= '1';
        wait for 12 ns;
        clr <= '0'; load <= '1';

        wait for 12 ns;
        load <= '0'; sb <= '1';
        wait for 12 ns;
        sb <= '0'; loadP <= '1';

        wait for 12 ns;
        loadP <= '0'; sb <= '1';
        wait for 12 ns;
        sb <= '0'; loadP <= '1';

        wait for 12 ns;
        loadP <= '0'; sb <= '1';
        wait for 12 ns;
        sb <= '0'; loadP <= '1';

        wait for 12 ns;
        loadP <= '0'; sb <= '1';
        wait for 12 ns;
        sb <= '0'; loadP <= '1';

        wait for 12 ns;
        loadP <= '0'; sb <= '1';

        wait for 20 ns;
        loadP <= '0'; sb <= '0';


      wait;
   end process;

END;

抱歉，我没有对代码进行注释以便更好地理解。我知道这很难遵循，但我希望有人会这样做。我还将附上我正在关注的顺序乘法器的图形图像，电路设计。

4 by 4 binary sequential multiplier circuit

4 by 4 binary sequential multiplier circuit - more

Answer 1

好吧，确实是测试台中的某些东西出了问题。我在实验室和同学们一起解决了这个问题。非常感谢您的帮助。

p.s。我所做的只是将最底部的测试台中的一些时序值更改为加载和移位位发生的时间，我让它开始工作。

无法让 VHDL 顺序乘法器正确乘法

Can't get VHDL Sequential Multiplier to Multiply correctly

vhdl

sequential

multiplication

circuit