VHDL工程中使用buffer的错误

Question

我是 VHDL 的初学者。我正在尝试实施一个简单的项目，但出现了一些错误。第一个是关于使用缓冲区。

这是我的实体代码：

entity Demultiplexer is
Port ( A : in  STD_LOGIC;
       S : in  STD_LOGIC_VECTOR (2 downto 0);
       I0 : out  STD_LOGIC;
       I1 : out  STD_LOGIC;
       I2 : out  STD_LOGIC;
       I3 : out  STD_LOGIC;
       I4 : out  STD_LOGIC;
       I5 : out  STD_LOGIC;
       I6 : out  STD_LOGIC;
       I7 : out  STD_LOGIC);
end Demultiplexer;

这是我的架构：

architecture Behavioral of Demultiplexer is
begin
    I0 <= A WHEN S = "000" ELSE
    I1 <= A WHEN S = "001" ELSE
    I2 <= A WHEN S = "010" ELSE
    I3 <= A WHEN S = "011" ELSE
    I4 <= A WHEN S = "100" ELSE
    I5 <= A WHEN S = "101" ELSE
    I6 <= A WHEN S = "110" ELSE
    I7 <= A WHEN S = "111";
end Behavioral;

这是错误列表

ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments- 1\Demultiplexer.vhd" Line 49: Cannot read from 'out' object i1 ; use   'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 49: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 50: Cannot read from 'out' object i2 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 50: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 51: Cannot read from 'out' object i3 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 51: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 52: Cannot read from 'out' object i4 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 52: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 53: Cannot read from 'out' object i5 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 53: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 54: Cannot read from 'out' object i6 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 54: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 55: Cannot read from 'out' object i7 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 55: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:854 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 45: Unit <behavioral> ignored due to previous   errors.

Answer 1

您的条件分配有误。语法是

i0 <= a when s = "000" else other_value;  -- whatever your code is supposed to do
i1 <= a when s = "001" else other_value;
...

错误消息（有点误导）是由下一行中的 i1 赋值引起的：

i0 <= a when s = "000" else i1 ...

这是对代码的理解（直到它完全摆脱困境），这意味着您正在尝试从 VHDL 2008 之前不支持的 out 信号中读取。

VHDL工程中使用buffer的错误

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