Blind/ground 未使用的测试平台端口

Question

我得到了顶级模块，包括在测试台文件中实例化的子模块。子模块本身非常自由，因此当我测试顶层模块时，我只需要引入很少的信号并跟踪很少的输出，但是顶层模块还有很多其他端口。

我可以向这些引脚（不考虑它们的大小、类型）提供一些 "default"/"undefined" 信号（和接收器）吗？

我现在有 2 种方法解决这个问题，要么取出子模块进行测试（好吧，但我想在顶级模块中测试它），要么为输入和输入编写适当的 "zero" 输入引入输出信号（还有很多工作）。

在 Vivado 2015 中使用 VHDL

好的，这就是测试平台

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity tb_FIR_v0_3 is
end tb_FIR_v0_3;

architecture Behavioral of tb_FIR_v0_3 is   
shared variable C_S00_AXI_DATA_WIDTH : integer := 32;
shared variable C_S00_AXI_ADDR_WIDTH : integer := 7;

component FIR_v0_3 is
    generic (
        C_S00_AXI_DATA_WIDTH    : integer   := 32;
        C_S00_AXI_ADDR_WIDTH    : integer   := 7
    );
    port (
        fir_clk     : in  std_logic;
        fir_x_in    : in  std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
        fir_y_out   : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
        fir_d_out   : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
        -- User ports ends

        s00_axi_aclk    : in std_logic;
        s00_axi_aresetn : in std_logic;
        s00_axi_awaddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
        s00_axi_awprot  : in std_logic_vector(2 downto 0);
        s00_axi_awvalid : in std_logic;
        s00_axi_awready : out std_logic;
        s00_axi_wdata   : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
        s00_axi_wstrb   : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
        s00_axi_wvalid  : in std_logic;
        s00_axi_wready  : out std_logic;
        s00_axi_bresp   : out std_logic_vector(1 downto 0);
        s00_axi_bvalid  : out std_logic;
        s00_axi_bready  : in std_logic;
        s00_axi_araddr  : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
        s00_axi_arprot  : in std_logic_vector(2 downto 0);
        s00_axi_arvalid : in std_logic;
        s00_axi_arready : out std_logic;
        s00_axi_rdata   : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
        s00_axi_rresp   : out std_logic_vector(1 downto 0);
        s00_axi_rvalid  : out std_logic;
        s00_axi_rready  : in std_logic
    );
end component FIR_v0_3;

signal e_clk     : std_logic := '1' ;
signal e_reset   : std_logic := '1' ;
signal e_x_in    : std_logic_vector (31 downto 0);
signal e_y_out   : std_logic_vector (31 downto 0);
signal e_d_out   : std_logic_vector (31 downto 0);

signal s00_axi_awready   : std_logic;
signal s00_axi_wready    : std_logic;
signal s00_axi_bresp     : std_logic_vector(1 downto 0);
signal s00_axi_bvalid    : std_logic;
signal s00_axi_arready   : std_logic;
signal s00_axi_rdata     : std_logic_vector(32-1 downto 0);
signal s00_axi_rresp     : std_logic_vector(1 downto 0);
signal s00_axi_rvalid    : std_logic;

signal s00_axi_aclk     : std_logic := '0';
signal s00_axi_aresetn  : std_logic;
signal s00_axi_awaddr   : std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
signal s00_axi_awprot   : std_logic_vector(2 downto 0);
signal s00_axi_awvalid  : std_logic := '0';
signal s00_axi_wdata    : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
signal s00_axi_wstrb    : std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
signal s00_axi_wvalid   : std_logic := '0';
signal s00_axi_bready   : std_logic := '0';
signal s00_axi_araddr   : std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
signal s00_axi_arprot   : std_logic_vector(2 downto 0);
signal s00_axi_arvalid  : std_logic := '0';
signal s00_axi_rready   : std_logic := '0';

begin   
inst_FIR_v0_3 : FIR_v0_3
generic map (
    C_S00_AXI_DATA_WIDTH => 32,
    C_S00_AXI_ADDR_WIDTH => 7
)
port map (
    -- Users to add ports here
    fir_clk     => e_clk,
    fir_x_in    => e_x_in,
    fir_y_out   => e_y_out,
    fir_d_out   => e_d_out,

    -- Ports of Axi Slave Bus Interface S00_AXI
    s00_axi_aclk     => s00_axi_aclk,
    s00_axi_aresetn  => e_reset,
    s00_axi_awaddr   => ( others => '0' ),
    s00_axi_awprot   => ( others => '0' ),
    s00_axi_awvalid  => s00_axi_awvalid,
    s00_axi_awready  => s00_axi_awready,
    s00_axi_wdata    => ( others => '0' ),
    s00_axi_wstrb    => ( others => '0' ),
    s00_axi_wvalid   => s00_axi_wvalid,
    s00_axi_wready   => s00_axi_wready,
    s00_axi_bresp    => s00_axi_bresp,
    s00_axi_bvalid   => s00_axi_bvalid,
    s00_axi_bready   => s00_axi_bready,
    s00_axi_araddr   => ( others => '0' ),
    s00_axi_arprot   => ( others => '0' ),
    s00_axi_arvalid  => s00_axi_arvalid,
    s00_axi_arready  => s00_axi_arready,
    s00_axi_rdata    => s00_axi_rdata,
    s00_axi_rresp    => s00_axi_rresp,
    s00_axi_rvalid   => s00_axi_rvalid,
    s00_axi_rready   => s00_axi_rready
);

process
    variable count : integer := 0;
begin

    if ( count = 0 ) then
        -- e_reset <= '0'; -- VALUES NOT INITIATED PROPERLY, FUCKER ? ... With the non-stop, pop pop and stainless steel (DMX)
        e_x_in <= x"00000000";
    end if;

    if ( count = 3 ) then
        -- e_reset <= '1';
    end if;

    if ( count = 3 ) then
        e_x_in <= x"00000001";
    end if;

    if ( count = 5 ) then
        e_x_in <= x"00000000";
    end if;

    if ( count = 8 ) then
        e_x_in <= x"00000000";
    end if;

    e_clk <= not(e_clk);
    wait for 0.5 ns;
    count := count + 1;
    if( (count = 60) ) then
        count := 0;
    end if;
end process;


end Behavioral;

我懒得为每个AXI input/output端口创建信号，然后将它们一一连接。我可以避免以某种方式创建这 21 个信号 ...

signal s00_axi_awready   : std_logic;
signal s00_axi_wready    : std_logic;
signal s00_axi_bresp     : std_logic_vector(1 downto 0);
signal s00_axi_bvalid    : std_logic;
signal s00_axi_arready   : std_logic;
....
...

然后连接它们？像这样...

s00_axi_wvalid   => s00_axi_wvalid,
s00_axi_wready   => s00_axi_wready,
s00_axi_bresp    => s00_axi_bresp,
s00_axi_bvalid   => s00_axi_bvalid,
s00_axi_bready   => s00_axi_bready,

是否有任何 "universal" in/out 信号表明我会绑定到不重要的引脚，因为我不能让实例的端口处于未连接状态（据我所知和尝试过）。

Answer 1

如果我对问题的理解正确，port 定义中的输入可以有默认值，并且输出可以在实例化中保持未连接状态。例如：

entity ShiftRegister is
    Generic (
        WIDTH : integer
    );
    Port (
        clk : in  STD_LOGIC;
        enable : in  STD_LOGIC := '1';
        serial_in : in  STD_LOGIC := '0';
        parallel_out : out  STD_LOGIC_VECTOR (WIDTH-1 downto 0);
    );
end ShiftRegister;

...

    SR : entity work.ShiftRegister
    Generic map (
        WIDTH : integer => 8
    )
    Port map(
        clk => serial_clk,
        serial_in => serial_data_in
    );

在本例中，寄存器将一直处于启用状态，实体不会输出任何内容。在这种情况下不是一个非常有用的实例化，但我认为这回答了你的问题！

Blind/ground 未使用的测试平台端口

Blind/ground unused testbench ports

vhdl

xilinx

vivado