Xst:3002 在 Verilog 中

Question

我正在 ISE 14.7 上创建一个递减计数器。我设置了一个异步复位（rst_n），每当它变为0时，计数器的值将设置为init_value。

但是当我合成代码时，出现警告：Xst3002

代码：

`timescale 1ns / 1ps

module downcounter(value, borrow, clk, rst_n, decrease, init_value, limit);
    output reg [3:0]value;              //value of counter
    output reg borrow;                  //borrow indicator
    input clk, rst_n, decrease;         //clock; active low reset; to decrease
    input [3:0]init_value, limit;       //initial value; counter limit

    reg [3:0]value_tmp, init_value_tmp; //for always block

    //Combinational logic
    always @(value or decrease or limit or borrow)begin
        if(~decrease) begin value_tmp = value; borrow = 0; end      //if decrease is 0, the counter stops counting down.
        else begin
            if(value == 0)begin value_tmp = limit; borrow = 1; end  //if the value is 0, the next value would be the limit.
            else begin value_tmp = value + 4'b1111; borrow = 0; end //Ex: limit = 9, so that value(now) = 0, then value(next) = 9 in decimal.
        end
    end
    //Sequentical logic
    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) value <= init_value_tmp;             //asynchronous reset. set the value to initial value
        else begin
            value <= value_tmp;
        end
    end
endmodule

和警告消息：

WARNING:Xst:3002 - This design contains one or more registers/latches that are directly incompatible with the Spartan6 architecture. The two primary causes of this is either a register or latch described with both an asynchronous set and asynchronous reset, or a register or latch described with an asynchronous set or reset which however has an initialization value of the opposite polarity (i.e. asynchronous reset with an initialization value of 1). While this circuit can be built, it creates a sub-optimal implementation in terms of area, power and performance. For a more optimal implementation Xilinx highly recommends one of the following:
      1) Remove either the set or reset from all registers and latches
         if not needed for required functionality
      2) Modify the code in order to produce a synchronous set
         and/or reset (both is preferred)
      3) Ensure all registers have the same initialization value as the
         described asynchronous set or reset polarity
      4) Use the -async_to_sync option to transform the asynchronous
         set/reset to synchronous operation
         (timing simulation highly recommended when using this option)
Please refer to http://www.xilinx.com search string "Spartan6 asynchronous set/reset" for more details.

List of register instances with asynchronous set and reset: value_0 in unit value_1 in unit value_2 in unit value_3 in unit

似乎是因为[3:0]值出现警告。但我对此一无所知。我试图将异步重置更改为 0，警告消失了。但这不是我想要的。

Answer 1

此设计存在一些问题。首先，init_value_tmp 似乎没有设置值。其次，由于它是非常数，Spartan-6 架构可能无法使用内置重置功能实际重置为该值。更改 value <= init_value_tmp; 以便它为 value.

分配一些有意义的常量

至于异步重置，它似乎是有效的，但由于我没有 Spartan-6 设备，你必须综合它并自己尝试。我担心的是，无论您使用什么常量值，都可能运行进入您之前收到的极性警告。同步复位很可能 "just work" 因为它只是 CLB 中进入数据输入的多路复用器。

编辑：关于使用非常量重置值的目标，您几乎必然需要同步重置（这更像是一种赋值而不是重置):

always @(posedge clk) begin
    if(~rst_n) value <= init_value_tmp;
    else begin
        value <= value_tmp;
    end
end

Xst:3002 在 Verilog 中

Xst:3002 in Verilog

verilog

synthesis