添加在 for-loop verilog 中不起作用

Question

我正在尝试编写将两个浮点数相乘的 Verilog 代码。试图通过移动和添加来乘以两个尾数是我运行遇到麻烦的地方。问题是，当我尝试更新 "shift and add" 变量 C_m_tmp 时，没有任何反应 (C_m_tmp = C_m_tmp + tmp;)。我省略了与我的问题无关的任何代码块。谁能告诉我哪里出错了？

`timescale 1ns / 1ps
module float_mult( A_m, B_m, C_m);
    input [22:0]A_m, B_m;
    output [45:0]C_m;

    reg [45:0] C_m_tmp;
    reg [22:0] A_m_tmp;
    reg [22:0] B_m_tmp;
    reg [45:0] tmp;
    reg [4:0]i;

    initial begin         
        assign C_m_tmp = 46'b0;
    end
 //need to remove the leading one from mantissas
always@ (A_m) begin
    A_m_tmp = A_m >> 1;
    A_m_tmp = A_m_tmp ^ 23'b10000000000000000000000;
end
always@ (B_m) begin
    B_m_tmp = B_m >> 1;
    B_m_tmp = B_m_tmp ^ 23'b10000000000000000000000;
 end
 always@(A_m_tmp, B_m_tmp) begin
    for (i=0; i <=22; i=i+1)
        if (B_m_tmp[i] == 1)begin
            tmp =  {23'b0,A_m_tmp};
            tmp = tmp <<i;
            C_m_tmp = C_m_tmp + tmp;    //this line does nothing
        end
 end
    always@(C_m_tmp)begin
        if (C_m_tmp[45] == 1) begin
            C_e_tmp = C_e_tmp + 1'b1;
        end

    end


    assign C_e = C_e_tmp + 8'b01111111;
    assign C_m = C_m_tmp[45:23];
    assign C_s = C_s_tmp;        

endmodule

Answer 1

initial begin         
assign C_m_tmp = 46'b0;
end

不需要上面的代码。

相反，您可以

always@(C_m_tmp)begin
C_m_tmp = 'b0;
        if (C_m_tmp[45] == 1) begin
            C_e_tmp = C_e_tmp + 1'b1;
        end

    end

添加在 for-loop verilog 中不起作用

addition not working in for-loop verilog

for-loop

verilog

addition

vivado