VHDL 开关正确代码
VHDL-Switches Proper Code
你好,我想完成这个
(可点击)
而且我已经写了这段代码,它是否正确?
因为我在 MAX+PLUS II 上的编译器没有显示任何错误...
LIBRARY IEEE;
USE IEE.STD_LOGIC_1164.ALL;
ENTITY alarm IS PORT
(ON/OFF,MOTION_SENSOR,.LIGHT_SENSOR,.SOUND_SENSOR,.CAMERA_SENSOR,.IP_SENSOR,.TEMPERATURE_SENSOR: IN STD_LOGIC;
SENSOR_SIRINE,SENSOR_LIGHT:OUT STD_LOGIC);
END alarm;
ARCHITECTURE LEITOURGEIA OF alarm IS
BEGIN
if (ON/OFF='1' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then
SENSOR_LIGHT<='1';
SENSOR_SIRINE<='1';
ELSE IF (ON/OFF='0' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then
SENSOR_LIGHT<='1';
SENSOR_SIRINE<='0';
ELSE
SENSOR_LIGHT<='0';
SENSOR_SIRINE<='0';
END IF
END LEITOURGEIA;
这是您的代码作为有效 VHDL 的近似值:
library ieee;
use ieee.std_logic_1164.all;
entity alarm is
port (
on_off, motion_sensor, light_sensor,
sound_sensor, camera_sensor, ip_sensor,
temperature_sensor: in std_logic;
sensor_sirine, sensor_light: out std_logic
);
end alarm;
architecture leitourgeia of alarm is
begin
unlabelled:
process (on_off, motion_sensor, light_sensor, sound_sensor,
camera_sensor, ip_sensor, temperature_sensor)
begin
if on_off = '1' and
(motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or
camera_sensor = '1' or ip_sensor = '1' or temperature_sensor='1') then
sensor_light <= '1';
sensor_sirine <= '1';
elsif on_off = '0' and
(motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or
camera_sensor = '1' or ip_sensor = '1' or temperature_sensor = '1') then
sensor_light <= '1';
sensor_sirine <= '0';
else
sensor_light <= '0';
sensor_sirine <= '0';
end if;
end process;
end leitourgeia;
我缩进了它,修复了一些拼写错误,使事物成为有效的标识符,将 if 语句放在一个过程中并使 else if
成为 elsif
,并去掉了两组多余的括号.
现在分析、阐述和模拟。
这个架构也是如此:
architecture foo of alarm is
signal alarm_light: std_logic;
begin
alarm_light <= motion_sensor or sound_sensor or light_sensor or
camera_sensor or ip_sensor or temperature_sensor;
sensor_light <= alarm_light;
sensor_sirine <= '1' when alarm_light = '1' and on_off = '1' else
'0';
end architecture foo;
它更类似于引用的示意图。
而这个更类似于引用的原理图:
architecture fum of alarm is
signal alarm_light: std_logic;
begin
alarm_light <= motion_sensor or sound_sensor or light_sensor or
camera_sensor or ip_sensor or temperature_sensor;
sensor_light <= alarm_light;
sensor_sirine <= on_off and alarm_light;
end architecture fum;
你好,我想完成这个
而且我已经写了这段代码,它是否正确? 因为我在 MAX+PLUS II 上的编译器没有显示任何错误...
LIBRARY IEEE;
USE IEE.STD_LOGIC_1164.ALL;
ENTITY alarm IS PORT
(ON/OFF,MOTION_SENSOR,.LIGHT_SENSOR,.SOUND_SENSOR,.CAMERA_SENSOR,.IP_SENSOR,.TEMPERATURE_SENSOR: IN STD_LOGIC;
SENSOR_SIRINE,SENSOR_LIGHT:OUT STD_LOGIC);
END alarm;
ARCHITECTURE LEITOURGEIA OF alarm IS
BEGIN
if (ON/OFF='1' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then
SENSOR_LIGHT<='1';
SENSOR_SIRINE<='1';
ELSE IF (ON/OFF='0' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then
SENSOR_LIGHT<='1';
SENSOR_SIRINE<='0';
ELSE
SENSOR_LIGHT<='0';
SENSOR_SIRINE<='0';
END IF
END LEITOURGEIA;
这是您的代码作为有效 VHDL 的近似值:
library ieee;
use ieee.std_logic_1164.all;
entity alarm is
port (
on_off, motion_sensor, light_sensor,
sound_sensor, camera_sensor, ip_sensor,
temperature_sensor: in std_logic;
sensor_sirine, sensor_light: out std_logic
);
end alarm;
architecture leitourgeia of alarm is
begin
unlabelled:
process (on_off, motion_sensor, light_sensor, sound_sensor,
camera_sensor, ip_sensor, temperature_sensor)
begin
if on_off = '1' and
(motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or
camera_sensor = '1' or ip_sensor = '1' or temperature_sensor='1') then
sensor_light <= '1';
sensor_sirine <= '1';
elsif on_off = '0' and
(motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or
camera_sensor = '1' or ip_sensor = '1' or temperature_sensor = '1') then
sensor_light <= '1';
sensor_sirine <= '0';
else
sensor_light <= '0';
sensor_sirine <= '0';
end if;
end process;
end leitourgeia;
我缩进了它,修复了一些拼写错误,使事物成为有效的标识符,将 if 语句放在一个过程中并使 else if
成为 elsif
,并去掉了两组多余的括号.
现在分析、阐述和模拟。
这个架构也是如此:
architecture foo of alarm is
signal alarm_light: std_logic;
begin
alarm_light <= motion_sensor or sound_sensor or light_sensor or
camera_sensor or ip_sensor or temperature_sensor;
sensor_light <= alarm_light;
sensor_sirine <= '1' when alarm_light = '1' and on_off = '1' else
'0';
end architecture foo;
它更类似于引用的示意图。
而这个更类似于引用的原理图:
architecture fum of alarm is
signal alarm_light: std_logic;
begin
alarm_light <= motion_sensor or sound_sensor or light_sensor or
camera_sensor or ip_sensor or temperature_sensor;
sensor_light <= alarm_light;
sensor_sirine <= on_off and alarm_light;
end architecture fum;