将此原理图转换为verilog代码，编译不成功

Question

下面是完整的代码。我只想将下面的原理图实现到 Verilog 代码中。只是有点困惑，我是否可以在一个 always 块中编写组合逻辑和顺序逻辑。其次，敏感列表需要时钟脉冲和输入变化。这是一个手工解决的解决方案，但现在我想将它带入 Verilog 并在 Verilog 中实现它并查看输出。

module Q4a(
input x,
 input clock,
output z
);
reg z; 
reg y1,y2;
reg d1,d2;
//wire x;
//wire clock;

always @(x,y1,y2)
begin
d1=(~x)&y2;
d2=x;
z=x&y1; 
end

always @(clock)
begin 
//y1<=(~x)&y2;
//y2<=x;
//z<=x&y1;
y1<=d1;
y2<=d2;

end
endmodule

Answer 1

x和z在Verilog中有特殊含义，变量名最好用别的东西。

module Q4a(
 input x,
 input clock,
 output reg z //Just declare as reg here
);

reg y1,y2;
reg d1,d2;

// Use automatic sensitivity list
always @* begin
  d1=(~x)&y2;
  d2=x;
  z=x&y1; 
end

//Filp-flops use `posedge` to make edge sensitive
always @(posedge clock) begin 
  y1<=d1;
  y2<=d2;
end

endmodule

这在 EDA Playground 上的 vcs 中编译。但回顾一下，我会写成：

module Q4a(
 input      x,
 input      clock,
 output reg z
);

reg y1,y2;

always @* begin
  z = x & y1; 
end

always @(posedge clock) begin 
  y1 <= ~x & y2;
  y2 <= x;
end

endmodule

Answer 2

不需要一直用always begin ... end，可以直接用赋值语句写组合电路

见下面的代码：

module Q4a (
             input wire x,
             input wire clock,
             input wire rst_n,
             output wire z
        );

wire d1;
reg  y1;
reg  y2;

assign d1 = ~x & y2;
assign z  =  x & y1;

always @ (posedge clock or negedge rst_n)
begin
  if(rst_n) begin
    y1 <= 1'b0;
    y2 <= 1'b0;
  end else begin
    y1 <= d1;
    y2 <= x;  // x is d2 too.
  end
end

endmodule

或者你也可以这样做，

assign z  =  x & y1;

always @ (posedge clock or negedge rst_n)
begin
  if(rst_n) begin
    y1 <= 1'b0;
    y2 <= 1'b0;
  end else begin
    y1 <= ~x & y2;
    y2 <= x;  // x is d2 too.
  end
end

将此原理图转换为verilog代码，编译不成功

Converting this schematic to verilog code, compile unsuccessful

verilog

sequential