了解分支预测
Understanding branch prediction
有一些关于分支预测的问题，我无法自信地认为 out.Assume 我必须使用静态分支预测器。
- At which stage of the pipeline should branch prediction happen?
- How to know that a prediction has gone wrong? How does the datapath come to know that a misprediction has happened?
- If it comes to know that a misprediction has happened, how does it send the signal to take up the not-taken branch?
- After it has gone wrong, I have to take up that address that was not taken earlier. In the meanwhile, what if some memory-write or register-write has happened? How to prevent it from happening?
即使建议一些带有数据路径的适当引用，这也会非常有帮助。提前致谢。
我想可能有很多不同的机制，但有一些快速的答案：
- 分支预测当然需要在指令解码之前发生，在获取阶段。否则，您将解码不正确的指令。
- 你通常会用预测的分支指令给出额外的信息，比如预测的目标。分支会被执行，如果真实目标与预测目标不匹配，就需要flush pipe。
- 这真的取决于实施。如果分支被执行，你可以使用真正的目标，就像一个没有预测到的分支。
- 你肯定需要一个恢复的机制，或者等分支解决了，直到你写出结果。这会浪费一些时间，但不会像未预测的分支那么多。
我花时间阅读了 Cortex-A8 的参考手册：http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/DDI0344K_cortex_a8_r3p2_trm.pdf
来自第 5.1 节：
The processor contains program flow prediction hardware, also known as
branch prediction. With program flow prediction disabled, all taken
branches incur a 13-cycle penalty. With program flow prediction
enabled, all mispredicted branches incur a 13-cycle penalty.
基本上这意味着静态分支预测总是假定分支为假。这与 PowerPC 不同，后者具有 "special instructions" 用于提示处理器有关 taken/not-taken 个分支（后缀 +/-）。
来自第 1.3.1 节：
The instruction fetch unit predicts the instruction stream, fetches
instructions from the L1 instruction cache, and places the fetched
instructions into a buffer for consumption by the decode pipeline.
- 第一阶段的指令提取进行预测。
来自第 7.6.2 节：
An instruction can remain in the pipeline between being fetched and
being executed. Because there can be several unresolved branches in
the pipeline, instruction fetches are speculative, meaning there is
no guarantee that they are executed. A branch or exceptional
instruction in the code stream can cause a pipeline flush, discarding the currently fetched instructions. Fetches or instruction
table walks that begin without an empty pipeline are marked
speculative. If the pipeline contains any instruction up to the
point of branch and exception resolution, then the pipeline is
considered not empty.
我将此解释为在处理分支时没有任何内容到达执行阶段。如果发生预测错误，正如在 Instruction Execute 中执行分支时发现的那样，流水线中的所有指令都是 "flushed"。他们永远不会被处决。那应该回答问题 2 和 4。不太确定 "marking" 是如何执行的。
- 我不知道它是如何发送信号的。据我所知，参考手册并未涵盖该部分。猜猜这是魔法。
（作为记录，我找到了 PowerPC 参考手册 (e500/e600) 由于有许多指令时序示例，我习惯于更容易理解。）
有一些关于分支预测的问题，我无法自信地认为 out.Assume 我必须使用静态分支预测器。
- At which stage of the pipeline should branch prediction happen?
- How to know that a prediction has gone wrong? How does the datapath come to know that a misprediction has happened?
- If it comes to know that a misprediction has happened, how does it send the signal to take up the not-taken branch?
- After it has gone wrong, I have to take up that address that was not taken earlier. In the meanwhile, what if some memory-write or register-write has happened? How to prevent it from happening?
即使建议一些带有数据路径的适当引用，这也会非常有帮助。提前致谢。
我想可能有很多不同的机制，但有一些快速的答案：
- 分支预测当然需要在指令解码之前发生，在获取阶段。否则，您将解码不正确的指令。
- 你通常会用预测的分支指令给出额外的信息，比如预测的目标。分支会被执行，如果真实目标与预测目标不匹配，就需要flush pipe。
- 这真的取决于实施。如果分支被执行，你可以使用真正的目标，就像一个没有预测到的分支。
- 你肯定需要一个恢复的机制，或者等分支解决了，直到你写出结果。这会浪费一些时间，但不会像未预测的分支那么多。
我花时间阅读了 Cortex-A8 的参考手册：http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/DDI0344K_cortex_a8_r3p2_trm.pdf
来自第 5.1 节：
The processor contains program flow prediction hardware, also known as branch prediction. With program flow prediction disabled, all taken branches incur a 13-cycle penalty. With program flow prediction enabled, all mispredicted branches incur a 13-cycle penalty.
基本上这意味着静态分支预测总是假定分支为假。这与 PowerPC 不同，后者具有 "special instructions" 用于提示处理器有关 taken/not-taken 个分支（后缀 +/-）。
来自第 1.3.1 节：
The instruction fetch unit predicts the instruction stream, fetches instructions from the L1 instruction cache, and places the fetched instructions into a buffer for consumption by the decode pipeline.
- 第一阶段的指令提取进行预测。
来自第 7.6.2 节：
An instruction can remain in the pipeline between being fetched and being executed. Because there can be several unresolved branches in the pipeline, instruction fetches are speculative, meaning there is no guarantee that they are executed. A branch or exceptional instruction in the code stream can cause a pipeline flush, discarding the currently fetched instructions. Fetches or instruction table walks that begin without an empty pipeline are marked speculative. If the pipeline contains any instruction up to the point of branch and exception resolution, then the pipeline is considered not empty.
我将此解释为在处理分支时没有任何内容到达执行阶段。如果发生预测错误，正如在 Instruction Execute 中执行分支时发现的那样，流水线中的所有指令都是 "flushed"。他们永远不会被处决。那应该回答问题 2 和 4。不太确定 "marking" 是如何执行的。
- 我不知道它是如何发送信号的。据我所知，参考手册并未涵盖该部分。猜猜这是魔法。
（作为记录，我找到了 PowerPC 参考手册 (e500/e600) 由于有许多指令时序示例，我习惯于更容易理解。）