使用 VHDL 在 Testbench 中实现顶级实体

Question

我是 VHDL 和硬件世界的新手。我正在尝试使用顶级层次结构制作一个计数和比较示例，并使用测试平台对其进行测试，然后在 ISIM 上查看结果。

这是我的框图草图：

所以我最终得到了这 3 个 vhd 源文件：

Counter.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Count_src is
    Port ( CLK   : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           S     : out  STD_LOGIC_VECTOR (3 downto 0));
end Count_src;

architecture Behavioral of Count_src is
signal count : STD_LOGIC_VECTOR (3 downto 0);

begin
process (Reset, CLK)
    begin
        if Reset = '1' then                             -- Active high reset
            count <= "0000";                            -- Clear count to 0
        elsif (rising_edge(CLK)) then                   -- Positive edge
            count <= count + "0001";                    -- increment count
        end if;
    end process;
S <= count;                                             -- Export count
end Behavioral;

比较

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity Compare_src is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           S : out  STD_LOGIC);
end Compare_src;

architecture Behavioral of Compare_src is

begin

    S <= '1' when (A = B) else          -- Test if A and B are same
         '0';                           -- Set when S is different

end Behavioral;

CountCompare（顶级）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CountCompare_src is
    Port ( Clock : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           Value : in  STD_LOGIC_VECTOR (3 downto 0);
           Flag : out  STD_LOGIC);
end CountCompare_src;

architecture Behavioral of CountCompare_src is

-- COMPONENT DECLERATIONS
component counter is
    port ( CLK   : in std_logic;
           Reset : in std_logic;
           S     : out std_logic_vector(3 downto 0)
         );
end component;

component compare is
    port (A : in std_logic_vector(3 downto 0);
          B : in std_logic_vector(3 downto 0);
          S : out std_logic
         );
end component;

-- Component Spesification and Binding
for all : counter use entity work.Count_src(behavioral);
for all : compare use entity work.Compare_src(behavioral);

-- Internal Wires
signal count_out : std_logic_vector(3 downto 0);

begin

-- Component instantiation

C1: counter PORT MAP ( Reset => Reset,
                       CLK => Clock,
                       S => count_out
                     );

C2: compare PORT MAP ( A => count_out,
                       B => Value,
                       S => Flag
                     );

end Behavioral;

为了测试设计，我编写了一个测试平台，如下所示：

测试台

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY TopLevelTester_tb IS
END TopLevelTester_tb;

ARCHITECTURE behavior OF TopLevelTester_tb IS 

   --Input and Output definitions.
   signal Clock : std_logic := '0';
    signal Reset : std_logic := '0';
   signal Value : std_logic_vector(3 downto 0) := "1000";
    signal Flag  : std_logic;

   -- Clock period definitions
   constant clk_period : time := 1 ns;

BEGIN

   -- Instantiate the Unit Under Test (UUT)
   uut: entity work.CountCompare_src PORT MAP 
    (
        Clock => Clock,
        Reset => Reset,
        Value => Value
    );

   proc: process
   begin
       Clock <= '0';
       wait for clk_period/2;
       Clock <= '1';
       wait for clk_period/2;   
   end process;

END;

当我模拟行为模型时，ISIM 弹出，但我在 Compare Flag 上没有看到任何变化。这是 ISIM 的 ss：

我在这里错过了什么？为什么 Flag 没有改变？

谨致问候。

Answer 1

你有两个问题，都在你的测试平台上。

首先是您永远不会重置计数器中的计数，它始终是“U”或“X”（在您增加它之后）。

第二个是测试平台中的直接实体实例化缺少正式标志输出到实际标志信号的关联：

begin

uut: 
    entity work.countcompare_src 
        port map (
            clock => clock,
            reset => reset,
            value => value,
            flag => flag
        );

proc: 
    process
    begin
        clock <= '0';
        wait for clk_period/2;
        clock <= '1';
        wait for clk_period/2;  
        if now > 20 ns then
            wait;
        end if; 
    end process;

stimulus:
    process
    begin
        wait for 1 ns;
        reset <= '1';
        wait for 1 ns;
        reset <= '0';
        wait;
    end process;

解决这两件事，你会得到：

使用 VHDL 在 Testbench 中实现顶级实体

Realizing Top Level Entity in Testbench using VHDL

vhdl

simulation

test-bench