VHDL中过程语句的基础知识

Question

在 xilinx 的测试台上，我认识到像

这样的语句

 clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;

据我所知，当参数改变时，进程就会执行。但是，在这里，我们不声明任何参数。为什么这段代码有效？在什么情况下？而且，为什么我们必须使用像 "clk_process:" 这样的标签或在端口映射中。很抱歉这是一个非常基本的问题:( 即使是简短的解释也足够了

Answer 1

IEEE Std 1076-2008, 10.2 等待声明：

The wait statement causes the suspension of a process statement or a procedure.

11.3 流程说明：

A process statement defines an independent sequential process representing the behavior of some portion of the design.

第 12 段：

The execution of a process statement consists of the repetitive execution of its sequence of statements. After the last statement in the sequence of statements of a process statement is executed, execution will immediately continue with the first statement in the sequence of statements.

返回 10.2，第 8 段：

The execution of a wait statement causes the time expression to be evaluated to determine the timeout interval. It also causes the execution of the corresponding process statement to be suspended, where the corresponding process statement is the one that either contains the wait statement or is the parent (see 4.3) of the procedure that contains the wait statement. The suspended process will resume, at the latest, immediately after the timeout interval has expired.

回到 11.3，第 4 段：

If a process sensitivity list appears following the reserved word process, then the process statement is assumed to contain an implicit wait statement as the last statement of the process statement part; this implicit wait statement is of the form

wait on sensitivity_list ;

（涵盖进程敏感列表的情况）。

你所说的标签就是标签。标签基本上是可选的（特别是在这里，尽管有些地方可能需要标签）。

10.1最后一段（10.顺序语句）：

All sequential statements may be labeled. Such labels are implicitly declared at the beginning of the declarative part of the innermost enclosing process statement or subprogram body.

11.1最后一段（11.并发语句）：

All concurrent statements may be labeled. Such labels are implicitly declared at the beginning of the declarative part of the innermost enclosing entity declaration, architecture body, block statement, or generate statement.

（而process语句就是并发语句，见11.1第2段）

11.3，第 2 段：

process_statement ::= 
    [ process_label : ]
        [ postponed ] process [ ( process_sensitivity_list ) ] [ is ] 
              process_declarative_part
        begin
            process_statement_part
        end [ postponed ] process [ process_label ] ;

其中方括号括起一个可选项目。（见1.3.2句法说明）

Answer 2

testbench中经常使用这样的过程。该过程用于生成时钟，应在测试设计中使用该时钟。你只需要定义一个"clk_period"比如1us，得到一个1MHz的时钟命名为"clk".

非常重要，此代码不可综合，仅用于模拟！

"Tag" "clk_process"只是进程名，你可以随便叫。

VHDL中过程语句的基础知识

Basics about process statement in VHDL

vhdl