Verilog FSM 控制器和数据路径

Question

下面的代码显示了一个有限状态机，它控制一个单独的数据路径模块来查找两个 4 位数字的 GCD。我目前收到以下错误，我不确定为什么。也许它们是由于某些我不知道的语法造成的：

ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD123/Controller.v" Line 48: Syntax error near ";".
ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD123/Controller.v" Line 59: Syntax error near ";".
ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD123/Controller.v" Line 62: Syntax error near ";".

遇到错误的代码如下：

module Controller(start,reset,x_sel,y_sel,xlty,xgty,xequaly,clk);

    input   start,clk, reset, xlty, xgty,xequaly;
    output x_sel,y_sel;

    
    // Declare state register
    reg     [1:0]state;
    
    // Declare states
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
    
    
    debounce startd(.clock(clk),.noisy(start),.clean(clean_start));
    
    always @ (posedge clk or posedge reset) begin
        if (reset)
            state <= S0;
        else
            case (state)
                S0:
                    if (clean_start)
                        state <= S1;
                    else
                        state <= S0;
                S1:
                    x_sel <= 0;
                    y_sel <= 0;
                    state <= S2;
                S2:
                    if (xlty)
                        state <= S3;
                    else if(xgty)
                        state <= S4;
                    else if(xequaly)
                        state <= S5;
                S3:
                    y_sel <= 1;
                    state <= S2;
                S4:
                    x_sel <= 1;
                    state <= S2;
                S5:
                    state <= S0;

            endcase
    end
    
endmodule

有错误的行是 y_sel <= 0; 在 S1 状态，state <= S2; 在 S4 状态和 state <= S2; 在 S3状态。

Answer 1

连续语句周围需要 begin/end 个关键字：

module Controller(start,reset,x_sel,y_sel,xlty,xgty,xequaly,clk);
input   start,clk, reset, xlty, xgty,xequaly;
output x_sel,y_sel;


// Declare state register
reg     [1:0]state;

// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;


debounce startd(.clock(clk),.noisy(start),.clean(clean_start));

always @ (posedge clk or posedge reset) begin
    if (reset)
        state <= S0;
    else
        case (state)
            S0:
                if (clean_start)
                    state <= S1;
                else
                    state <= S0;
            S1:
              begin
                x_sel <= 0;
                y_sel <= 0;
                state <= S2;
              end
            S2:
                if (xlty)
                    state <= S3;
                else if(xgty)
                    state <= S4;
                else if(xequaly)
                    state <= S5;
            S3:
              begin
                y_sel <= 1;
                state <= S2;
              end
            S4:
              begin
                x_sel <= 1;
                state <= S2;
              end
            S5:
                state <= S0;

        endcase
end

endmodule

Verilog FSM 控制器和数据路径

Verilog FSM controller and datapath

verilog

hdl

fsm