VHDL 程序无法编译

Question

我正在尝试用执行以下操作的结构方式创建一个 VHDL ALU： 1)加法 2)减法 3）逻辑与 4)逻辑或

我是运行我在 Quartus II 中的代码，它在编译时发现了一些错误。这是我的代码：

library ieee;
use ieee.std_logic_1164.all;
use work.basic_func.all;

entity askhsh1 is
port
(   a : in std_logic_vector(15 downto 0);
    b : in std_logic_vector(15 downto 0);
    coin : in std_logic;
    coout : out std_logic;
    s : in std_logic_vector(15 downto 0);
    d : in std_logic_vector(15 downto 0);
    result : out std_logic;
    operator : in std_logic;
    binvert : in std_logic;
    ainvert : in std_logic);

 end askhsh1;

 architecture structure of askhsh1 is 
    signal c : std_logic_vector(1 to 15);
    signal result : std_logic_vector(15 downto 0);
 component myAND
    port (in1, in2: in std_logic; out1: out std_logic);
end component;
component myOR
    port (in1, in2: in std_logic; out1: out std_logic);
end component;
component myXOR
    port (in1, in2: in std_logic; out1: out std_logic);
end component;
component fullader
    port (cin, x, y : in std_logic; 
            s, cout : out std_logic);
end component;
begin 
U1 : myAND port map (a, b, result) when (operator = '0') else T1 : myOR port map (a, b, result) when (operator = '1')
else (stage0 : fullader port map (coin, a(0), b(0), s(0), c(1));
       stage1 : fullader port map (c(1), a(1), b(1), s(1), c(2));
        stage2 : fullader port map (c(2), a(2), b(2), s(2), c(3));
        stage3 : fullader port map (c(3), a(3), b(3), s(3), c(4));
        stage4 : fullader port map (c(4), a(4), b(4), s(4), c(5));
        stage5 : fullader port map (c(5), a(5), b(5), s(5), c(6));
        stage6 : fullader port map (c(6), a(6), b(6), s(6), c(7));
        stage7 : fullader port map (c(7), a(7), b(7), s(7), c(8));
        stage8 : fullader port map (c(8), a(8), b(8), s(8), c(9));
        stage9 : fullader port map (c(9), a(9), b(9), s(9), c(10));
        stage10 : fullader port map (c(10), a(10), b(10), s(10), c(11));
        stage11 : fullader port map (c(11), a(11), b(11), s(11), c(12));
        stage12 : fullader port map (c(12), a(12), b(12), s(12), c(13));
        stage13 : fullader port map (c(13), a(13), b(13), s(13), c(14));
        stage14 : fullader port map (c(14), a(14), b(14), s(14), c(15));
        stage15 : fullader port map (c(15), a(15), b(15), s(15), coout);) when (operator = '2' and binvert = '0' and ainvert = '0')

else  (stage0 : fullader port map ('1', a(0), not b(0), s(0), c(1));
       stage1 : fullader port map (c(1), a(1), not b(1), s(1), c(2));
        stage2 : fullader port map (c(2), a(2), not b(2), s(2), c(3));
        stage3 : fullader port map (c(3), a(3), not b(3), s(3), c(4));
        stage4 : fullader port map (c(4), a(4), not b(4), s(4), c(5));
        stage5 : fullader port map (c(5), a(5), not b(5), s(5), c(6));
        stage6 : fullader port map (c(6), a(6), not b(6), s(6), c(7));
        stage7 : fullader port map (c(7), a(7), not b(7), s(7), c(8));
        stage8 : fullader port map (c(8), a(8), not b(8), s(8), c(9));
        stage9 : fullader port map (c(9), a(9), not b(9), s(9), c(10));
        stage10 : fullader port map (c(10), a(10), not b(10), s(10), c(11));
        stage11 : fullader port map (c(11), a(11), not b(11), s(11), c(12));
        stage12 : fullader port map (c(12), a(12), not b(12), s(12), c(13));
        stage13 : fullader port map (c(13), a(13), not b(13), s(13), c(14));
        stage14 : fullader port map (c(14), a(14), not b(14), s(14), c(15));
        stage15 : fullader port map (c(15), a(15), not b(15), s(15), coout);) when (operator = '2' and binvert = '1' and ainvert = '0')

else (stage0 : fullader port map ('1', not a(0), b(0), s(0), c(1));
       stage1 : fullader port map (c(1), not a(1), b(1), s(1), c(2));
        stage2 : fullader port map (c(2), not a(2), b(2), s(2), c(3));
        stage3 : fullader port map (c(3), not a(3), b(3), s(3), c(4));
        stage4 : fullader port map (c(4), not a(4), b(4), s(4), c(5));
        stage5 : fullader port map (c(5), not a(5), b(5), s(5), c(6));
        stage6 : fullader port map (c(6), not a(6), b(6), s(6), c(7));
        stage7 : fullader port map (c(7), not a(7), b(7), s(7), c(8));
        stage8 : fullader port map (c(8), not a(8), b(8), s(8), c(9));
        stage9 : fullader port map (c(9), not a(9), b(9), s(9), c(10));
        stage10 : fullader port map (c(10), not a(10), b(10), s(10), c(11));
        stage11 : fullader port map (c(11), not a(11), b(11), s(11), c(12));
        stage12 : fullader port map (c(12), not a(12), b(12), s(12), c(13));
        stage13 : fullader port map (c(13), not a(13), b(13), s(13), c(14));
        stage14 : fullader port map (c(14), not a(14), b(14), s(14), c(15));
        stage15 : fullader port map (c(15), not a(15), b(15), s(15),        coout);) when (operator = '2' and ainvert = '1' and binvert = '0')
else P1 : myXOR port map (a, b, result) when (operator = '3');
end structure;

包裹 basic_func 在这里：

 library ieee;
 use ieee.std_logic_1164.all;

 package basic_func is 
component myAND
    port (in1, in2: in std_logic; out1: out std_logic);
end component;
component myOR
    port (in1, in2: in std_logic; out1: out std_logic);
end component;
component myXOR
    port (in1, in2: in std_logic; out1: out std_logic);
end component;
component fullader
    port (cin, x, y : in std_logic; 
            s, cout : out std_logic);
end component;
end package basic_func;


  library ieee;
  use ieee.std_logic_1164.all;
  entity myAND is
port (in1, in2: in std_logic; out1: out std_logic);
end myAND;
  architecture modeland of myAND is
begin
    out1 <= in1 and in2;
  end modeland;


  library ieee;
  use ieee.std_logic_1164.all;
  entity myOR is
  port (in1, in2: in std_logic; out1: out std_logic);
  end myOR;
  architecture modelor of myOR is
begin
    out1 <= in1 or in2;
    end modelor;


   library ieee;
   use ieee.std_logic_1164.all;
   entity myXOR is
   port (in1, in2: in std_logic; out1: out std_logic);
   end myXOR;
   architecture modelxor of myXOR is
   begin
     out1 <= in1 xor in2;
   end modelxor;


   library ieee;
   use ieee.std_logic_1164.all;
   entity myfullader is
   port (cin, x, y : in std_logic; 
            s, cout : out std_logic);
   end myfullader;
  architecture modelfulla of myfullader is
   begin
     s <= x xor y xor cin;
     cout <= (x and y) or (cin and x) or (cin and y);
   end modelfulla;

感谢任何帮助

Answer 1

您解决 select 功能块的不同输出（加法等）问题的方法无效：

U1 : myAND port map (a, b, result) when (operator = '0') else T1 : myOR port map (a, b, result) when (operator = '1') -- and so on

请记住，您描述的是硬件。您在这里尝试做的是实例化 不同的 硬件，具体取决于 operator，它会在运行时间内发生变化。您需要做的是实例化 all 功能块，然后使用您的 operator 来复用这些功能块的 one 的输出块到你的输出。很难给出一个可以准确复制的示例，但是 select 其中一个输出的一般方法看起来像这样（其中 operator 是一个 integer range 0 to 2）：

process (operator, adder_output, and_output, or_output) 
begin
  case (operator) is
    when 0 => result <= and_output;
    when 1 => result <= or_output;
    when 2 => result <= adder_output;
  end case;
end process;

还有几点需要说明。

您的 operator 被定义为 std_logic，而您正在尝试检查它是否为 '2'。看起来要实现您拥有的运算符数量，您应该将此输入定义为 integer。完成此操作后，您将根据整数文字测试此输入，它看起来像 2、 而不是 '2'。假设您有 3 个运算符，我会输入 operator : in integer range 0 to 2。
您将 result 定义为 std_logic 端口和 std_logic_vector 信号。目前尚不清楚您真正想要什么，但我怀疑您应该将 result 端口设置为 std_logic_vector，然后删除信号。
您正在使用位置关联实例化实体。通常不建议这样做。你在哪里：
```
stage0 : fullader port map (coin, a(0), b(0), s(0), c(1));
```
您可以改用命名关联:
```
stage0 : fullader port map (
  cin => coin,
  x => a(0),
  y => b(0),
  s => s(0),
  cout => c(1)
);
```
这可以防止有人更改端口列表时出现错误，并使代码更具可读性。
我建议让代码更加结构化，这样你就可以创建一个使用你的 fulladder 实体创建 8 位加法器的实体，然后你可以更干净地实例化这个顶层的 8 位加法器。这将使您的代码更清楚发生了什么。
如果您确实需要有条件地实例化一个实体，您可以使用 generate 语句：
```
SomeLabel : if (my_condition = true) generate
  stage0 : fullader port map (
    cin => coin,
    x => a(0),
    y => b(0),
    s => s(0),
    cout => c(1)
  );
end generate;
```
同样，我认为这不是您在这种情况下应该使用的，因为 generate 是一个编译时构造，并且您希望行为在运行-时间.

VHDL 程序无法编译

VHDL program doesn' t compile

vhdl

quartus