设计的内存单元不起作用，无法读取内存 0
Designed memory unit doesn't work, cannot read memory 0
module InstructionMemory (input clk,
input[31:0] PC,
output reg[31:0] Inst_out
);
reg[31:0] instructions [0:2**32-1];
initial
$readmemb("InstructionMemory.txt",instructions);
always@(posedge clk)
begin
Inst_out = instructions[PC];
end
endmodule
这是我InstructionMemory.txt的文字：
00000000000000010000000011110000
假设，
您在
处有错字
reg[31:0] instructions [0: 2**32 -1];
应该是，
reg[31:0] instructions [0: (2*32) -1];
因为2**32 = 4294967296，不可能这么长
在那之后我修改了你的 InstructionMemory.txt 文件和 运行 模拟它工作正常，见下面的代码。
带测试平台的 Verilog 代码：
module InstructionMemory (input clk,
input[31:0] PC,
output reg[31:0] Inst_out
);
reg [31:0] instructions [0 : (2*32) -1];
initial
begin
$readmemb("InstructionMemory.txt",instructions);
end
always@(posedge clk)
begin
Inst_out <= instructions[PC];
end
endmodule
module tb;
reg clk;
reg [31:0] PC;
wire [31:0] Inst_out;
integer j;
InstructionMemory InstructionMemory_u0(clk, PC, Inst_out);
always #5 clk = ~clk;
initial
begin
$monitor("PC = %d and Inst_Out = %d", PC, Inst_out);
clk = 1'b0;
PC = 32'b0;
for(j=0;j<64;j=j+1)
begin
@(posedge clk)
PC = j;
end
#100 $finish;
end
endmodule
你的记忆InstructionMemory.txt
00000000000000000000000000000000
00000000000000000000000000000001
00000000000000000000000000000010
00000000000000000000000000000011
00000000000000000000000000000100
00000000000000000000000000000101
00000000000000000000000000000110
00000000000000000000000000000111
00000000000000000000000000001000
00000000000000000000000000001001
00000000000000000000000000001010
00000000000000000000000000001011
00000000000000000000000000001100
00000000000000000000000000001101
00000000000000000000000000001110
00000000000000000000000000001111
00000000000000000000000000010000
00000000000000000000000000010001
00000000000000000000000000010010
00000000000000000000000000010011
00000000000000000000000000010100
00000000000000000000000000010101
00000000000000000000000000010110
00000000000000000000000000010111
00000000000000000000000000011000
00000000000000000000000000011001
00000000000000000000000000011010
00000000000000000000000000011011
00000000000000000000000000011100
00000000000000000000000000011101
00000000000000000000000000011110
00000000000000000000000000011111
00000000000000000000000000100000
00000000000000000000000000100001
00000000000000000000000000100010
00000000000000000000000000100011
00000000000000000000000000100100
00000000000000000000000000100101
00000000000000000000000000100110
00000000000000000000000000100111
00000000000000000000000000101000
00000000000000000000000000101001
00000000000000000000000000101010
00000000000000000000000000101011
00000000000000000000000000101100
00000000000000000000000000101101
00000000000000000000000000101110
00000000000000000000000000101111
00000000000000000000000000110000
00000000000000000000000000110001
00000000000000000000000000110010
00000000000000000000000000110011
00000000000000000000000000110100
00000000000000000000000000110101
00000000000000000000000000110110
00000000000000000000000000110111
00000000000000000000000000111000
00000000000000000000000000111001
00000000000000000000000000111010
00000000000000000000000000111011
00000000000000000000000000111100
00000000000000000000000000111101
00000000000000000000000000111110
00000000000000000000000000111111
模拟：
QuestaSim-64 qverilog 10.4 Compiler 2014.12 Dec 2 2014
Start time: 10:18:08 on May 16,2016
qverilog mem.v
-- Compiling module InstructionMemory
-- Compiling module tb
Top level modules:
tb
Reading pref.tcl
# 10.4
# vsim -lib work tb -c -do "run -all; quit -f" -appendlog -l qverilog.log -vopt
# ** Note: (vsim-8009) Loading existing optimized design _opt1
# // Questa Sim-64
# // Version 10.4 linux_x86_64 Dec 2 2014
# //
# // Copyright 1991-2014 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.
# //
# Loading work.tb(fast)
# run -all
# PC = 0 and Inst_Out = x
# PC = 0 and Inst_Out = 0
# PC = 1 and Inst_Out = 0
# PC = 2 and Inst_Out = 1
# PC = 3 and Inst_Out = 2
# PC = 4 and Inst_Out = 3
# PC = 5 and Inst_Out = 4
# PC = 6 and Inst_Out = 5
# PC = 7 and Inst_Out = 6
# PC = 8 and Inst_Out = 7
# PC = 9 and Inst_Out = 8
# PC = 10 and Inst_Out = 9
# PC = 11 and Inst_Out = 10
# PC = 12 and Inst_Out = 11
# PC = 13 and Inst_Out = 12
# PC = 14 and Inst_Out = 13
# PC = 15 and Inst_Out = 14
# PC = 16 and Inst_Out = 15
# PC = 17 and Inst_Out = 16
# PC = 18 and Inst_Out = 17
# PC = 19 and Inst_Out = 18
# PC = 20 and Inst_Out = 19
# PC = 21 and Inst_Out = 20
# PC = 22 and Inst_Out = 21
# PC = 23 and Inst_Out = 22
# PC = 24 and Inst_Out = 23
# PC = 25 and Inst_Out = 24
# PC = 26 and Inst_Out = 25
# PC = 27 and Inst_Out = 26
# PC = 28 and Inst_Out = 27
# PC = 29 and Inst_Out = 28
# PC = 30 and Inst_Out = 29
# PC = 31 and Inst_Out = 30
# PC = 32 and Inst_Out = 31
# PC = 33 and Inst_Out = 32
# PC = 34 and Inst_Out = 33
# PC = 35 and Inst_Out = 34
# PC = 36 and Inst_Out = 35
# PC = 37 and Inst_Out = 36
# PC = 38 and Inst_Out = 37
# PC = 39 and Inst_Out = 38
# PC = 40 and Inst_Out = 39
# PC = 41 and Inst_Out = 40
# PC = 42 and Inst_Out = 41
# PC = 43 and Inst_Out = 42
# PC = 44 and Inst_Out = 43
# PC = 45 and Inst_Out = 44
# PC = 46 and Inst_Out = 45
# PC = 47 and Inst_Out = 46
# PC = 48 and Inst_Out = 47
# PC = 49 and Inst_Out = 48
# PC = 50 and Inst_Out = 49
# PC = 51 and Inst_Out = 50
# PC = 52 and Inst_Out = 51
# PC = 53 and Inst_Out = 52
# PC = 54 and Inst_Out = 53
# PC = 55 and Inst_Out = 54
# PC = 56 and Inst_Out = 55
# PC = 57 and Inst_Out = 56
# PC = 58 and Inst_Out = 57
# PC = 59 and Inst_Out = 58
# PC = 60 and Inst_Out = 59
# PC = 61 and Inst_Out = 60
# PC = 62 and Inst_Out = 61
# PC = 63 and Inst_Out = 62
# PC = 63 and Inst_Out = 63
# ** Note: $finish : mem.v(39)
# Time: 735 ns Iteration: 0 Instance: /tb
# End time: 10:18:09 on May 16,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
Your output is one cycle late due to flop used in Reading of Instruction.
如果你真的想使用 2**32 指令集，你必须声明相同的内存。
编辑：
关于PC的信息，
让我们以 8051 为例，它是一个真正的 uController，您可以在其中找到 16 位长的 PC 大小。所以它可以访问程序地址 0x0000 到 0xFFFF，总共 64K 字节的代码。然而，并非 8051 的所有成员都安装了整个 64K 字节的片上 ROM。它用于可扩展内存使用。
module InstructionMemory (input clk,
input[31:0] PC,
output reg[31:0] Inst_out
);
reg[31:0] instructions [0:2**32-1];
initial
$readmemb("InstructionMemory.txt",instructions);
always@(posedge clk)
begin
Inst_out = instructions[PC];
end
endmodule
这是我InstructionMemory.txt的文字：
00000000000000010000000011110000
假设， 您在
处有错字reg[31:0] instructions [0: 2**32 -1];
应该是，
reg[31:0] instructions [0: (2*32) -1];
因为2**32 = 4294967296，不可能这么长
在那之后我修改了你的 InstructionMemory.txt 文件和 运行 模拟它工作正常，见下面的代码。
带测试平台的 Verilog 代码：
module InstructionMemory (input clk,
input[31:0] PC,
output reg[31:0] Inst_out
);
reg [31:0] instructions [0 : (2*32) -1];
initial
begin
$readmemb("InstructionMemory.txt",instructions);
end
always@(posedge clk)
begin
Inst_out <= instructions[PC];
end
endmodule
module tb;
reg clk;
reg [31:0] PC;
wire [31:0] Inst_out;
integer j;
InstructionMemory InstructionMemory_u0(clk, PC, Inst_out);
always #5 clk = ~clk;
initial
begin
$monitor("PC = %d and Inst_Out = %d", PC, Inst_out);
clk = 1'b0;
PC = 32'b0;
for(j=0;j<64;j=j+1)
begin
@(posedge clk)
PC = j;
end
#100 $finish;
end
endmodule
你的记忆InstructionMemory.txt
00000000000000000000000000000000
00000000000000000000000000000001
00000000000000000000000000000010
00000000000000000000000000000011
00000000000000000000000000000100
00000000000000000000000000000101
00000000000000000000000000000110
00000000000000000000000000000111
00000000000000000000000000001000
00000000000000000000000000001001
00000000000000000000000000001010
00000000000000000000000000001011
00000000000000000000000000001100
00000000000000000000000000001101
00000000000000000000000000001110
00000000000000000000000000001111
00000000000000000000000000010000
00000000000000000000000000010001
00000000000000000000000000010010
00000000000000000000000000010011
00000000000000000000000000010100
00000000000000000000000000010101
00000000000000000000000000010110
00000000000000000000000000010111
00000000000000000000000000011000
00000000000000000000000000011001
00000000000000000000000000011010
00000000000000000000000000011011
00000000000000000000000000011100
00000000000000000000000000011101
00000000000000000000000000011110
00000000000000000000000000011111
00000000000000000000000000100000
00000000000000000000000000100001
00000000000000000000000000100010
00000000000000000000000000100011
00000000000000000000000000100100
00000000000000000000000000100101
00000000000000000000000000100110
00000000000000000000000000100111
00000000000000000000000000101000
00000000000000000000000000101001
00000000000000000000000000101010
00000000000000000000000000101011
00000000000000000000000000101100
00000000000000000000000000101101
00000000000000000000000000101110
00000000000000000000000000101111
00000000000000000000000000110000
00000000000000000000000000110001
00000000000000000000000000110010
00000000000000000000000000110011
00000000000000000000000000110100
00000000000000000000000000110101
00000000000000000000000000110110
00000000000000000000000000110111
00000000000000000000000000111000
00000000000000000000000000111001
00000000000000000000000000111010
00000000000000000000000000111011
00000000000000000000000000111100
00000000000000000000000000111101
00000000000000000000000000111110
00000000000000000000000000111111
模拟：
QuestaSim-64 qverilog 10.4 Compiler 2014.12 Dec 2 2014
Start time: 10:18:08 on May 16,2016
qverilog mem.v
-- Compiling module InstructionMemory
-- Compiling module tb
Top level modules:
tb
Reading pref.tcl
# 10.4
# vsim -lib work tb -c -do "run -all; quit -f" -appendlog -l qverilog.log -vopt
# ** Note: (vsim-8009) Loading existing optimized design _opt1
# // Questa Sim-64
# // Version 10.4 linux_x86_64 Dec 2 2014
# //
# // Copyright 1991-2014 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.
# //
# Loading work.tb(fast)
# run -all
# PC = 0 and Inst_Out = x
# PC = 0 and Inst_Out = 0
# PC = 1 and Inst_Out = 0
# PC = 2 and Inst_Out = 1
# PC = 3 and Inst_Out = 2
# PC = 4 and Inst_Out = 3
# PC = 5 and Inst_Out = 4
# PC = 6 and Inst_Out = 5
# PC = 7 and Inst_Out = 6
# PC = 8 and Inst_Out = 7
# PC = 9 and Inst_Out = 8
# PC = 10 and Inst_Out = 9
# PC = 11 and Inst_Out = 10
# PC = 12 and Inst_Out = 11
# PC = 13 and Inst_Out = 12
# PC = 14 and Inst_Out = 13
# PC = 15 and Inst_Out = 14
# PC = 16 and Inst_Out = 15
# PC = 17 and Inst_Out = 16
# PC = 18 and Inst_Out = 17
# PC = 19 and Inst_Out = 18
# PC = 20 and Inst_Out = 19
# PC = 21 and Inst_Out = 20
# PC = 22 and Inst_Out = 21
# PC = 23 and Inst_Out = 22
# PC = 24 and Inst_Out = 23
# PC = 25 and Inst_Out = 24
# PC = 26 and Inst_Out = 25
# PC = 27 and Inst_Out = 26
# PC = 28 and Inst_Out = 27
# PC = 29 and Inst_Out = 28
# PC = 30 and Inst_Out = 29
# PC = 31 and Inst_Out = 30
# PC = 32 and Inst_Out = 31
# PC = 33 and Inst_Out = 32
# PC = 34 and Inst_Out = 33
# PC = 35 and Inst_Out = 34
# PC = 36 and Inst_Out = 35
# PC = 37 and Inst_Out = 36
# PC = 38 and Inst_Out = 37
# PC = 39 and Inst_Out = 38
# PC = 40 and Inst_Out = 39
# PC = 41 and Inst_Out = 40
# PC = 42 and Inst_Out = 41
# PC = 43 and Inst_Out = 42
# PC = 44 and Inst_Out = 43
# PC = 45 and Inst_Out = 44
# PC = 46 and Inst_Out = 45
# PC = 47 and Inst_Out = 46
# PC = 48 and Inst_Out = 47
# PC = 49 and Inst_Out = 48
# PC = 50 and Inst_Out = 49
# PC = 51 and Inst_Out = 50
# PC = 52 and Inst_Out = 51
# PC = 53 and Inst_Out = 52
# PC = 54 and Inst_Out = 53
# PC = 55 and Inst_Out = 54
# PC = 56 and Inst_Out = 55
# PC = 57 and Inst_Out = 56
# PC = 58 and Inst_Out = 57
# PC = 59 and Inst_Out = 58
# PC = 60 and Inst_Out = 59
# PC = 61 and Inst_Out = 60
# PC = 62 and Inst_Out = 61
# PC = 63 and Inst_Out = 62
# PC = 63 and Inst_Out = 63
# ** Note: $finish : mem.v(39)
# Time: 735 ns Iteration: 0 Instance: /tb
# End time: 10:18:09 on May 16,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
Your output is one cycle late due to flop used in Reading of Instruction.
如果你真的想使用 2**32 指令集，你必须声明相同的内存。
编辑：
关于PC的信息， 让我们以 8051 为例，它是一个真正的 uController，您可以在其中找到 16 位长的 PC 大小。所以它可以访问程序地址 0x0000 到 0xFFFF，总共 64K 字节的代码。然而，并非 8051 的所有成员都安装了整个 64K 字节的片上 ROM。它用于可扩展内存使用。