测试台输入 10500 语法错误

Question

我试图在 Quartus 中为两个输入 AND 门创建一个简单的 hello world 测试平台。我一直运行出现以下错误：

Error (10500): VHDL syntax error at Scott_2InputAndGate_Test.vhd(19) near text "IN"; expecting an identifier ("in" is a reserved keyword), or a string literal

我的代码：

--------------------------------------
------------TOP LEVEL ENTITY----------
--------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;


ENTITY s_2InputAndGate IS
    PORT(a, b : IN  std_logic;
            z : OUT std_logic);
END ENTITY s_2InputAndGate;


ARCHITECTURE behaviour OF s_2InputAndGate IS
    BEGIN
        z <= a AND b;

END ARCHITECTURE behaviour;


--------------------------------------
------------TESTBENCH-----------------
--------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;

--No Entity for TestBench;
ENTITY s_2InputAndGate_Test IS END;



--Line 10
--Line 11
--Line 12...etc



--Behaviour of the Test bench;
ARCHITECTURE behaviour OF s_2InputAndGate_Test IS

    SIGNAL A_test, B_test : IN  std_logic;   --lINE(19 - ERROR HERE!)
                    Z_test: OUT std_logic;

    BEGIN
        A_test <= 0;
        B_test <= 0;

        WAIT FOR 50ns;

        A_test <= 0;
        B_test <= 1;

    WAIT FOR 50ns;

        A_test <= 1;
        B_test <= 0;

        WAIT FOR 50ns;

        A_test <= 1;
        B_test <= 1;

        WAIT;
END ARCHITECTURE behaviour;

编译器似乎一直在抱怨测试台中的信号声明。我检查了语法，似乎找不到任何明显的问题。任何人都知道为什么这一行会阻止成功编译？

Answer 1

SIGNAL A_test, B_test : IN  std_logic;

信号没有方向。只需使用：

SIGNAL A_test, B_test : std_logic;

此外，您的行 Z_test: OUT std_logic; 无效。删除方向后，您可以将此信号声明与其他两个一起添加。

测试台输入 10500 语法错误

Testbench input 10500 Syntax Error

vhdl

quartus