菜鸟考官，不能犯错。（使用伊卡洛斯 Verilog）

Question

我一直在尝试获取这段我一时兴起的代码。在大多数情况下，我认为我确定模块本身没问题。它是抛出所有错误的测试台。

完整代码如下：

/*
Primitive code to control a stepper motor using FPGA
It will run as a seconds hand
9 June 2016
dwiref024
*/

module clock_divider(clock, reset, clock_div);

input clock;
input reset;

output clock_div;
reg [25:0]counter = 26'd0;

// Assuming a clock frequency of 40Mhz
// log2(40M) = 25.25
// Therefore 40MHz corresponds to MOD25
always@(posedge clock, negedge reset)   begin
    if(!reset) begin
        counter <= 26'd0;   
    end

    if(counter == 26'd40000000) begin
        counter <= 26'd0;
    end

    else begin
    counter <= counter + 1;
    end

end

assign clock_div = counter[24]; // Gives you a clock signal 'clock_div'of approximate frequency 1Hz

initial begin
    $dumpvars(0, clock, reset, counter);
end
endmodule

module count_seconds (
input clock_div, reset
);
reg [5:0]seconds = 6'd0;

always@(posedge clock_div, negedge reset) begin
    if (!reset) begin
        seconds <= 0;
    end
    else if (seconds == 6'd60) begin
        seconds <= 0;
    end

    else begin
        seconds <= seconds + 1;
    end
end
initial begin
    $dumpvars (0, clock_div, seconds);
end

endmodule

module get_servo(
input clock_div,
output reg servoPin = 0, 
output reg ding
);

always@(posedge clock_div)  begin
    if(clock_div)
        ding <= 1;
    else
        ding <= 0;
end
always@(ding)   begin

    if (ding) begin
        servoPin = 1'b1;
    end
    else servoPin = 1'b0;
end


initial begin
    $dumpvars (0, servoPin);
end

endmodule

module clk_tb;
reg clock;
reg reset;
reg servoPin;
reg clock_div;
reg ding;
initial begin
    clock = 0;
    reset = 0;  
    repeat(2) #10 clock = ~clock;
    reset = 1;
    forever #10 clock = ~clock; 
end

clock_divider DUT1 (clock, reset, clock_div);
get_servo DUT2 (clock_div, servoPin, ding);

initial begin
    servoPin = 1'b1;
    #1 clock_div = 1'b0;
    $finish;
end

endmodule

在运行

$ icarusverilog -o servo servo.v

我收到以下错误：

servo.v:105: error: reg clock_div; cannot be driven by primitives or continuous assignment.
servo.v:105: error: Output port expression must support continuous assignment.
servo.v:105:      : Port 3 (clock_div) of clock_divider is connected to clock_div
servo.v:106: error: reg servoPin; cannot be driven by primitives or continuous assignment.
servo.v:106: error: Output port expression must support continuous assignment.
servo.v:106:      : Port 2 (servoPin) of get_servo is connected to servoPin
servo.v:106: error: reg ding; cannot be driven by primitives or continuous assignment.
servo.v:106: error: Output port expression must support continuous assignment.
servo.v:106:      : Port 3 (ding) of get_servo is connected to ding
6 error(s) during elaboration.

我查看了这里的所有内容，看到了指定何时何地在测试台模块中使用 reg 以避免出现这种情况的问题：

<variable name> is not a valid l-value in foo

这是我遇到的第一个错误。为了避免它，我最终得到了这些。如果有人能指出这些错误的根本原因以及它们的来源，我也许能够解决这个问题并在此过程中学到一些新东西。

Answer 1

信号clock_div、servoPin由多个驱动程序驱动。您已将 servoPin 作为 get_servo 模块和测试台 clk_tb 本身的输出驱动。这是非法的。

关于clock_div，参考下图：

模块的输出必须连接到电线。这里clock_div是clock_divider模块的输出口，必须是线型。然后该输出线可用作您的逻辑输入以驱动 servoPin 模块。以下是您的测试平台代码的片段：

reg clock;
reg reset;
reg servoPin;
// reg clock_div; // remove this
wire clock_div_w, clock_div_w2;
assign clock_div_w2 = clock_div_w; // drive output from one module to input to another
//...
clock_divider DUT1 (clock, reset, clock_div_w); // wire output
get_servo DUT2 (clock_div_w2, servoPin, ding);  // another wire input
//...
initial begin
    // servoPin = 1'b1; // donot drive from here, module output
    #1 clock_div = 1'b0;
    $finish;
end

类似的说明适用于 ding 端口。

参考IEEE 1800-2012，第23.3.3节：

Each port connection shall be a continuous assignment of source to sink, where one connected item shall be a signal source and the other shall be a signal sink. The assignment shall be a continuous assignment from source to sink for input or output ports.

当端口在实例化中连接到任何其他端口时，它是一个常量赋值，因此它总是需要目标端口为网络。

有关详细信息，请参阅 Port connection rules question。

菜鸟考官，不能犯错。（使用伊卡洛斯 Verilog）

Rookie test bencher, can't make head or tail of errors. (Using Icarus Verilog)

verilog

hdl

servo

菜鸟考官，不能犯错。 （使用伊卡洛斯 Verilog）

Rookie test bencher, can't make head or tail of errors. (Using Icarus Verilog)

verilog

hdl

servo

菜鸟考官，不能犯错。（使用伊卡洛斯 Verilog）