我使用 IP 为 IEEE float ALU 编写了一个 VHDL 程序 - 语法错误

Question

显示语法错误：

(Error (10396): VHDL syntax error at project_alu.vhd(69): name used in construct must match previously specified name "alu")

Error (10523): Ignored construct mux4 at project_alu.vhd(76) due to previous errors

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity porjectalu is
port(a,b : in std_logic_vector(31 downto 0);
        sel: in std_logic_vector(1 downto 0);
        reslut : in std_logic_vector(31 downto 0);
        clk : in std_logic_vector );
end porjectalu;

architecture alu of projectalu is
component add
    PORT
    (
        clock       : IN STD_LOGIC ;
        dataa       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        datab       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        result      : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
end component;
component mul
    PORT
    (
        clock       : IN STD_LOGIC ;
        dataa       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        datab       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        result      : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
end component;
component sub
    PORT
    (
        clock       : IN STD_LOGIC ;
        dataa       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        datab       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        result      : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
end component;
component div
    PORT
    (
        clock       : IN STD_LOGIC ;
        dataa       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        datab       : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        result      : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
end component;
component mux4
    PORT
    (
        i0  : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        i2  : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        i3 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        i4  : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        sel1: in std_logic_vector (1 downto 0);
        out1: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
end component;

signal add1, sub1, mul1, div1 : std_logic_vector(31 downto 0);
begin
U0: add port map(clk, a, b, add1);
U1: sub port map (clk, a, b, sub1);
U2: mul port map (clk, a, b, mul1);
U3: div port map (clk, a, b, div1);
u5: mux4 port map (add1, sub1, mul1, div1, s1, result);
end projectalu ;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux4 is
    PORT
    (
        i0: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        i1: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        i2: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        i3: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        sel1: in std_logic_vector (1 downto 0);
        out1: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
end mux4;
architecture arch of mux4 is
begin
process(i0, i1, i2, i3, sel1)
begin
    case sel1 is 
        when "00" => out1 <= i0;
        when "01" => out1 <= i1;
        when "10" => out1 <= i2;
        when "11" => out1 <= i3;
        when others  => null;
    end case;
end process;
end arch;

Answer 1

你有

architecture alu of projectalu is
  -- declarations
begin
  -- code
end projectalu; -- Error here

最后一行应该是 end alu; 或 end architecture;。

我使用 IP 为 IEEE float ALU 编写了一个 VHDL 程序 - 语法错误

I wrote a VHDL program for IEEE float ALU using IP - syntax error

vhdl

intel-fpga