什么是 VHDL 中的多个常量驱动程序错误

Question

我正在为闪存接口开发一个 VHDL 程序。编译我的程序时出现此错误。

（可点击）

正如您在图片中看到的，两个信号（右侧）被 "xnor" 编辑，结果被分配给输出 (flash_oe)。

谁能描述一下这个错误信息是什么？

Answer 1

你在做这样的事吗？

ENTITY test IS
  PORT ( sig1, sig3 : IN BIT;
         sig2 : OUT BIT);
END test;
---------------------------
ARCHITECTURE test_arch of test is
BEGIN
  PROCESS(sig1)
  BEGIN
    sig2 <= '0';
  END process;

  PROCESS(sig3)
  BEGIN
    sig2 <= '1';
  END process;
END test_arch;

让我们测试这段代码：

ghdl -a test.vhd
ghdl -e test
ghdl -r test

我们收到此错误：

sig2
./test:error: several sources for unresolved signal
for signal: .test(test_arch).ghdl: compilation error

这与您在上面发布的那个类似，之所以出现是因为我的代码在两个不同的进程中为 sig2 赋值。如何将其实现到电路中？

也许有解决方法，我没有提供解决您问题的方法，因为我不知道您的代码是什么样子。

Answer 2

A Google 搜索 "Error (10028) altera" returns this Altera Quartus II help 作为第一个命中，说：

Can't resolve multiple constant drivers for net "<name>" at <location> (ID: 10028)

CAUSE:
In the current design, multiple constant (non-tri-state) drivers are contending for the specified net, which was created by Quartus II Integrated Synthesis to represent one or more signals. This condition usually occurs when a Verilog Design File (.v) or VHDL Design File (.vhd) contains multiple concurrent assignments to the same signal. Quartus II Integrated Synthesis attempted to resolve the electrically equivalent assignments, but cannot resolve the contending assignments into a single equivalent driver.

The message(s) immediately below this message indicate the constant drivers to the net that conflict with the net's first constant driver.

ACTION: Check the design for multiple concurrent assignments to the same signal.

情况是，在综合中，每个信号只能有一个驱动程序，而在仿真中，解析信号可以有多个，因此您可能会看到设计在仿真中通过了编译，但在综合中没有通过.

所以寻找 flash_oe 的多个驱动器。

什么是 VHDL 中的多个常量驱动程序错误

What is multiple constant driver error in VHDL

vhdl

quartus