VHDL 代码 IF 语句也使用了 With XXX select

Question

帮助我的 VHDL 代码尝试 select 使用 IF 语句将什么输入转到输出使用 WITH XXX Select

s 是 select d和e 用于 4 输入 y 是输出

帮助谢谢

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;



ENTITY mux_4_1 IS
PORT(
S : in STD_LOGIC;
d : IN STD_LOGIC_VECTOR (3 downto 0);
e : IN STD_LOGIC_VECTOR (3 downto 0);
y : OUT STD_LOGIC_VECTOR (0 to 6));



END mux_4_1;

ARCHITECTURE behavior OF mux_4_1 is
BEGIN
PROCESS(S,d,e)
BEGIN
   IF S = '0' THEN

      WITH d SELECT

      y <=      "1111110" WHEN "0000",--0
                "0110000" WHEN "0001",--1
                "1101101" WHEN "0010",--2
                "1111001" WHEN "0011",--3
                "0110011" WHEN "0100",--4
                "1011011" WHEN "0101",--5
                "1011111" WHEN "0110",--6
                "1110000" WHEN "0111",--7
                "1111111" WHEN "1000",--8
                "1111011" WHEN "1001",--9
                 "0000000" when others;



ELSE S = '1' THEN

      WITH e SELECT

      y <=      "1111110" WHEN "0000",--0
                "0110000" WHEN "0001",--1
                "1101101" WHEN "0010",--2
                "1111001" WHEN "0011",--3
                "0110011" WHEN "0100",--4
                "1011011" WHEN "0101",--5
                "1011111" WHEN "0110",--6
                "1110000" WHEN "0111",--7
                "1111111" WHEN "1000",--8
                "1111011" WHEN "1001",--9
                 "0000000" when others;


END IF;
END PROCESS;
END behavior;

Error (10500): VHDL syntax error at mux_4_1.vhd(23) near text "WITH"; expecting "end", or "(", or an identifier ("with" is a reserved keyword), or a sequential statement
Error (10500): VHDL syntax error at mux_4_1.vhd(25) near text "WHEN"; expecting ";"

Answer 1

从你给出的内容中我能看出的唯一错误是 else 语句后没有 then。

VHDL 代码 IF 语句也使用了 With XXX select

VHDL code IF statement using a With XXX select also

vhdl

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