运行使用计数器的 3 到 7 解码器

Question

我正在尝试运行我的 3 到 7 解码器使用来自我的计数器的输入，所有单独的代码运行都很好，但是结构代码正在放弃一些错误

这是我的计数器的程序

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity counter is  
   port(clk , CLR : in std_logic;
   Q : out std_logic_vector(2 downto 0) );    
end counter;

architecture archi of counter is

    signal tmp: std_logic_vector(2 downto 0);  

    begin      
    process (clk, CLR)   
         begin       

         if (CLR='1') then                  
             tmp <= "000";                       
         elsif (clk'event and clk='1') then  
              tmp <= tmp + 1;                     
          end if;        

     end process;   

     Q <= tmp;

 end archi;

这是解码器的程序：

library IEEE;

use IEEE.std_logic_1164.all;

entity led_inp is

    port (I : in std_logic_vector(2 downto 0) ;

    L : out std_logic_vector(6 downto 0) ) ;

end led_inp ;

architecture led_inp1 of led_inp is 

Begin    
    L(0) <= (not I(0)) and (not I(1)) and (not I(2));   
    L(1) <= (not I(0)) and (not I(1)) and I(2);
    L(2) <= (not I(0)) and I(1) and (not I(2));
    L(3) <= (not I(0)) and I(1) and I(2);
    L(4) <= I(0) and (not I(1)) and (not I(2));
    L(5) <= I(0) and (not I(1)) and I(2);
    L(6) <= I(0) and I(1) and (not I(2));
end led_inp1;

这是整个设计的结构格式：

library IEEE;

use IEEE.std_logic_1164.all;

-- the entity of the whole design block, here i have given the names of the ports as the ones which i have used in my individual components 

entity led_design is  
    port(clock,CLEAR :in std_logic;        
    L :out std_logic_vector(6 downto 0));   
end led_design; 

architecture led_design1 of led_design is 
-- declaring my counter as a component 
   component counter   
   port(clk, CLR : in std_logic;     
   Q : out std_logic_vector(2 downto 0) );
 end component ;

-- declaring my decoder as a component 

component led_inp 
    port (I : in std_logic_vector(2 downto 0) ;
    L : out std_logic_vector(6 downto 0)) ;
end component  ;

signal I:std_logic_vector(2 downto 0);
begin 
    -- The PORT MAPPING BEGINS 

    L1: counter port map(clk=>clock,CLR=>CLEAR,I(2)=>I(2),I(1)=>I(1),I(0)=>I(0)); 

    L2: led_inp port map(I(2)=>I(2),I(1)=>I(1),I(0)=>I(0),L(0)=>L(0),L(1)=>L(1),L(2)=>L(2),L(3)=>L(3),L(4)=>L(4),L(5)=>L(5),L(6)=>L(6));

    L1: counter port 

    map(clk=>clock,CLR=>CLEAR,I(2)=>h(2),I(1)=>h(1),I(0)=>h(0)); 
end led_design1;

这是出现的错误：错误
ncvhdl_p: *E,FMLBAD (led_count,85|44)：元素关联 87[4.3.3.2] 93[4.3.2.2] 的格式不正确的正式部分。错误：1，警告：0

Answer 1

注意符号 led_count 没有出现在您的 VHDL 设计描述中，那是文件名吗？

你在 led_design 中有两个标签 L1，它也缺少信号 h 的声明以匹配信号 I。（这也告诉你它没有在其他任何地方使用）。

两个 counter 关联列表（端口映射）都不匹配组件声明。修复这些问题后，您的代码就会分析。注意 h 未在其他任何地方使用。

阅读 Markdown help 以了解如何格式化代码，这太糟糕了。

由于缺乏正确的格式和无法理解错误，导致可以回答的人无法提供答案。

试试这个：

library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity counter is  
   port(clk , CLR : in std_logic;    
         Q : out std_logic_vector(2 downto 0) ); 
end counter;

architecture archi of counter is

    signal tmp: std_logic_vector(2 downto 0);  

begin  

    process (clk, CLR)   
    begin       

        if (CLR='1') then                
            tmp <= "000";        
        elsif (clk'event and clk='1') then      
            tmp <= std_logic_vector(unsigned(tmp) + 1);             
        end if;        

    end process;   

    Q <= tmp;

end archi;



library IEEE;
use IEEE.std_logic_1164.all;

entity led_inp is
    port (I : in std_logic_vector(2 downto 0) ;
          L : out std_logic_vector(6 downto 0) ) ;
end led_inp ;

architecture led_inp1 of led_inp is 

Begin 

    L(0) <= (not I(0)) and (not I(1)) and (not I(2));
    L(1) <= (not I(0)) and (not I(1)) and I(2);
    L(2) <= (not I(0)) and I(1) and (not I(2));
    L(3) <= (not I(0)) and I(1) and I(2);
    L(4) <= I(0) and (not I(1)) and (not I(2));
    L(5) <= I(0) and (not I(1)) and I(2);
    L(6) <= I(0) and I(1) and (not I(2));

end led_inp1;



 library IEEE;
 use IEEE.std_logic_1164.all;

 entity led_design is 
     port(clock,CLEAR :in std_logic;    
          L :out std_logic_vector(6 downto 0));
 end led_design; 

 architecture led_design1 of led_design is

     component counter   
         port(clk, CLR : in std_logic;     
             Q : out std_logic_vector(2 downto 0) );
     end component ;

     component led_inp 
         port (I : in std_logic_vector(2 downto 0) ;
               L : out std_logic_vector(6 downto 0)) ;
     end component  ;

     signal I:std_logic_vector(2 downto 0);
     signal h:std_logic_vector(2 downto 0);
begin 

L1: counter port map (
      clk=>clock,CLR=>CLEAR, Q => I); -- I(2)=>I(2),I(1)=>I(1),I(0)=>I(0)); 

L2: led_inp port map ( I(2)=>I(2),I(1)=>I(1),I(0)=>I(0),L(0)=>L(0),L(1)=>L(1),L(2)=>L(2),L(3)=>L(3),L(4)=>L(4),L(5)=>L(5),L(6)=>L(6));

L3: counter port map( clk=>clock,CLR=>CLEAR, Q => h);-- I(2)=>h(2),I(1)=>h(1),I(0)=>h(0));
-- ERROR 
--**ncvhdl_p: *E,FMLBAD (led_count,85|44): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2].
--  errors: 1, warnings: 0"**


end led_design1;

numeric_std 的 use 子句和类型转换使我能够使用符合 -1993 的工具（没有 std_logic_unsigned）。您的环境可能不需要这些更改。

请注意第二个计数器（连接到 h）现在标记为 L3 的输出不会去任何地方。

请注意，如果您只是修复第 85 行，错误也应该出现在第 83 行中。

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