如何选择 VHDL 中的顶级架构之一（从一个文件）？

Question

我在 conf_gate.vhd 中有 3 个主要的 vhdl top 架构。在每个架构中，我想选择两种实例化架构之一（取决于常量值）。我可以使用同一顶部的配置关键字来选择一种架构吗（conf_gate.vhd）？示例如下（配置语句在文件末尾）

Pastebin 3_architecture_vhdl

-- configuration gate
-- File: conf_gate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity xor_gate is
    generic(
        DATA_WIDTH : natural := 3
        );
    port( 
        a : in std_logic_vector(DATA_WIDTH-1 downto 0);
        b : in std_logic_vector(DATA_WIDTH-1 downto 0);
        c : out std_logic_vector(DATA_WIDTH-1 downto 0)

        );
end xor_gate;

architecture arch of xor_gate is

begin
    c <= a xor b;
end arch;

architecture not_arch of xor_gate is

begin
    c <= a xnor b;
end not_arch;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity or_gate is
    generic(
        DATA_WIDTH : natural := 3
        );
    port( 
        a : in std_logic_vector(DATA_WIDTH-1 downto 0);
        b : in std_logic_vector(DATA_WIDTH-1 downto 0);
        c : out std_logic_vector(DATA_WIDTH-1 downto 0)

        );
end or_gate;

architecture arch of or_gate is

begin
    c <= a or b;
end arch;

architecture not_arch of or_gate is

begin
    c <= a nor b;
end not_arch;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity and_gate is
    generic(
        DATA_WIDTH : natural := 3
        );
    port( 
        a : in std_logic_vector(DATA_WIDTH-1 downto 0);
        b : in std_logic_vector(DATA_WIDTH-1 downto 0);
        c : out std_logic_vector(DATA_WIDTH-1 downto 0)

        );
end and_gate;

architecture arch of and_gate is

begin
    c <= a and b;
end arch;

architecture not_arch of and_gate is

begin
    c <= a nand b;
end not_arch;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity conf_gate is
    generic(
        DATA_WIDTH : natural := 3
        );
    port( 
        a : in std_logic_vector(DATA_WIDTH-1 downto 0);
        b : in std_logic_vector(DATA_WIDTH-1 downto 0);
        c : out std_logic_vector(DATA_WIDTH-1 downto 0)

        );
end conf_gate;

architecture and_gate_arch of conf_gate is

constant negated : boolean := true ;

begin

negated_gate : if negated = true generate
    mod_inst : and_gate(not_arch)
        generic map (
         DATA_WIDTH => DATA_WIDTH
        )
        port map (
            a => a,
            b => b,
            c => c
        );
    end generate negated_gate;

gate : if negated = false generate
    mod_inst : entity work.and_gate(arch)
        generic map (
         DATA_WIDTH => DATA_WIDTH
        )
        port map (
            a => a,
            b => b,
            c => c
        );
    end generate gate;


end and_gate_arch;

architecture or_gate_arch of conf_gate is

constant negated : boolean := true ;

begin

negated_gate : if negated = true generate
    mod_inst : entity work.or_gate(not_arch)
        generic map (
         DATA_WIDTH => DATA_WIDTH
        )
        port map (
            a => a,
            b => b,
            c => c
        );
    end generate negated_gate;

gate : if negated = false generate
    mod_inst : entity work.or_gate(arch)
        generic map (
         DATA_WIDTH => DATA_WIDTH
        )
        port map (
            a => a,
            b => b,
            c => c
        );
    end generate gate;


end or_gate_arch;

architecture xor_gate_arch of conf_gate is

constant negated : boolean := true ;

begin

negated_gate : if negated = true generate
    mod_inst : entity work.xor_gate(not_arch)
        generic map (
         DATA_WIDTH => DATA_WIDTH
        )
        port map (
            a => a,
            b => b,
            c => c
        );
    end generate negated_gate;

gate : if negated = false generate
    mod_inst : entity work.xor_gate(arch)
        generic map (
         DATA_WIDTH => DATA_WIDTH
        )
        port map (
            a => a,
            b => b,
            c => c
        );
    end generate gate;


end xor_gate_arch;

configuration CONF of conf_gate is
    for and_gate_arch
        for mod_inst : entity work.and_gate
            use entity work.conf_gate;
        end for;
    end for;
end CONF;

Answer 1

组件绑定推迟到配置声明：

configuration conf of conf_gate is
    for and_gate_arch
        for negated_gate
            for mod_inst: and_gate
                use entity work.and_gate(not_arch);
            end for;
        end for;
   end for;
end configuration conf;

需要组件实例化：

architecture and_gate_arch of conf_gate is
    constant negated:  boolean := true ;
    component and_gate is
        generic ( DATA_WIDTH:  natural := 3 );
        port ( 
            a:  in  std_logic_vector(DATA_WIDTH - 1 downto 0);
            b:  in  std_logic_vector(DATA_WIDTH - 1 downto 0);
            c:  out std_logic_vector(DATA_WIDTH - 1 downto 0)
        );
    end component;
begin
negated_gate:  
    if negated = true generate
mod_inst:  
        -- entity work.and_gate (not_arch)
        and_gate
            generic map ( DATA_WIDTH => DATA_WIDTH )
            port map (
                a => a,
                b => b,
                c => c
            );
    end generate negated_gate;

gate:  
    if negated = false generate
mod_inst:  
        entity work.and_gate(arch)
            generic map ( DATA_WIDTH => DATA_WIDTH )
            port map (
                a => a,
                b => b,
                c => c
            );
    end generate gate;

end architecture and_gate_arch;

您应该知道综合供应商并未广泛支持配置声明。值得检查您的供应商支持的 VHDL 构造（例如 Xilinx Vivado 用户指南 901 以进行综合）。

替代方法是在组件实例化的封闭声明区域中提供配置规范。

参见 IEEE Std 1076-2008 3.4 配置声明和 7.3 配置规范。了解显式绑定指示（7.3.2 绑定指示）和默认绑定指示（7.3.3 默认绑定指示）之间的区别也很有用。

如何选择 VHDL 中的顶级架构之一（从一个文件）？

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